Searched refs:TEGRA124_CLK_PLL_M_UD (Results 1 – 7 of 7) sorted by relevance
346 #define TEGRA124_CLK_PLL_M_UD 313 macro
342 #define TEGRA124_CLK_PLL_M_UD 313 macro
69 clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>;83 clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>;90 clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>;
73 clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>;87 clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>;94 clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>;
69 clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>;83 clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>;150 clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>;164 clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>;231 clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>;245 clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>;
78 clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>;
1145 clks[TEGRA124_CLK_PLL_M_UD] = clk; in tegra124_pll_init()