| /openbmc/qemu/hw/timer/ |
| H A D | renesas_tmr.c | 37 REG8(TCSR, 2)
38 FIELD(TCSR, OSA, 0, 2)
39 FIELD(TCSR, OSB, 2, 2)
40 FIELD(TCSR, ADTE, 4, 2)
219 ret = FIELD_DP8(ret, TCSR, OSA, in tmr_read()
220 FIELD_EX8(tmr->tcsr[ch], TCSR, OSA)); in tmr_read()
221 ret = FIELD_DP8(ret, TCSR, OSB, in tmr_read()
222 FIELD_EX8(tmr->tcsr[ch], TCSR, OSB)); in tmr_read()
225 ret = FIELD_DP8(ret, TCSR, ADTE, in tmr_read()
226 FIELD_EX8(tmr->tcsr[ch], TCSR, ADTE)); in tmr_read()
[all …]
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| /openbmc/linux/Documentation/translations/zh_CN/arch/mips/ |
| H A D | ingenic-tcu.rst | 25 - 每个TCU通道都有自己的时钟源，可以通过 TCSR 寄存器设置通道的父级时钟
28 - 看门狗和OST硬件模块在它们的寄存器空间中也有相同形式的TCSR寄存器。
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| /openbmc/linux/Documentation/devicetree/bindings/clock/ |
| H A D | qcom,sm8550-tcsr.yaml | 7 title: Qualcomm TCSR Clock Controller on SM8550
13 Qualcomm TCSR clock control module provides the clocks, resets and
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| /openbmc/linux/Documentation/arch/mips/ |
| H A D | ingenic-tcu.rst | 19 different clocks (pclk, ext, rtc), gated, and reclocked, through their TCSR register.
21 - The watchdog and OST hardware blocks also feature a TCSR register with the same
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| /openbmc/linux/Documentation/devicetree/bindings/firmware/ |
| H A D | qcom,scm.yaml | 96 - description: phandle to TCSR hardware block
98 description: TCSR hardware block
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| /openbmc/linux/Documentation/devicetree/bindings/pci/ |
| H A D | qcom,pcie-ep.yaml | 49 description: Reference to a syscon representing TCSR followed by the two
55 - description: Syscon to TCSR system registers
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| /openbmc/linux/drivers/net/wan/ |
| H A D | hd64570.h | 92 #define TCSR 0x04 /* Control/Status */ macro
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| H A D | hd64572.h | 117 #define TCSR 0x206 /* Timer Control/Status Register */ macro
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| /openbmc/linux/Documentation/devicetree/bindings/soc/qcom/ |
| H A D | qcom,gsbi.yaml | 60 Phandle of TCSR syscon node.Required if child uses dma.
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| /openbmc/linux/Documentation/devicetree/bindings/remoteproc/ |
| H A D | qcom,q6v5.txt | 90 Definition: a phandle reference to a syscon representing TCSR followed
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| H A D | qcom,qcs404-cdsp-pil.yaml | 83 Phandle reference to a syscon representing TCSR followed by the
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| H A D | qcom,sdm845-adsp-pil.yaml | 83 Phandle reference to a syscon representing TCSR followed by the
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| H A D | qcom,sc7280-wpss-pil.yaml | 91 Phandle reference to a syscon representing TCSR followed by the
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| H A D | qcom,sc7280-adsp-pil.yaml | 79 Phandle reference to a syscon representing TCSR followed by the
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| H A D | qcom,msm8916-mss-pil.yaml | 116 - description: phandle to TCSR syscon region
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| H A D | qcom,msm8996-mss-pil.yaml | 117 - description: phandle to TCSR syscon region
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| /openbmc/linux/Documentation/devicetree/bindings/bus/ |
| H A D | qcom,ssc-block-bus.yaml | 87 - description: Phandle reference to a syscon representing TCSR
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| /openbmc/linux/Documentation/devicetree/bindings/phy/ |
| H A D | qcom,qusb2-phy.yaml | 83 Phandle to TCSR syscon register region.
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| H A D | qcom,sc8280xp-qmp-pcie-phy.yaml | 83 - description: phandle of TCSR syscon
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| /openbmc/linux/Documentation/devicetree/bindings/usb/ |
| H A D | ci-hdrc-usb2.yaml | 234 Phandler of TCSR node with two argument that indicate register
238 - description: phandle to TCSR node
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| /openbmc/linux/drivers/clk/qcom/ |
| H A D | Kconfig | 1007 tristate "SM8550 TCSR Clock Controller"
1011 Support for the TCSR clock controller on SM8550 devices.
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