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Searched refs:TCR (Results 1 – 5 of 5) sorted by relevance

/openbmc/qemu/hw/timer/
H A Drenesas_tmr.c32 REG8(TCR, 0)
33 FIELD(TCR, CCLR, 3, 2)
34 FIELD(TCR, OVIE, 5, 1)
35 FIELD(TCR, CMIEA, 6, 1)
36 FIELD(TCR, CMIEB, 7, 1)
208 ret = FIELD_DP8(ret, TCR, CCLR, in tmr_read()
209 FIELD_EX8(tmr->tcr[ch], TCR, CCLR)); in tmr_read()
210 ret = FIELD_DP8(ret, TCR, OVIE, in tmr_read()
211 FIELD_EX8(tmr->tcr[ch], TCR, OVIE)); in tmr_read()
212 ret = FIELD_DP8(ret, TCR, CMIEA, in tmr_read()
[all …]
/openbmc/qemu/hw/ppc/
H A Dtrace-events126 ppc4xx_fit(uint32_t ir, uint64_t tcr, uint64_t tsr) "ir %d TCR 0x%" PRIx64 " TSR 0x%" PRIx64
129 ppc4xx_pit(uint32_t ar, uint32_t ir, uint64_t tcr, uint64_t tsr, uint64_t reload) "ar %d ir %d TCR …
130 ppc4xx_wdt(uint64_t tcr, uint64_t tsr) "TCR 0x%" PRIx64 " TSR 0x%" PRIx64
/openbmc/u-boot/arch/powerpc/include/asm/
H A Dprocessor.h684 #define TCR SPRN_TCR /* Timer Control Register */ macro
/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dstart.S294 mtspr TCR,r0 /* disable all */
/openbmc/libcper/specification/document/
H A Dcper-json-specification.tex1181 tcr\_el1 & uint64 & Register TCR (EL1).\\
1219 tcr\_el2 & uint64 & Register TCR (EL2).\\
1249 tcr\_el3 & uint64 & Register TCR (EL3).\\