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Searched refs:TCG_TARGET_HAS_eqv_i32 (Results 1 – 14 of 14) sorted by relevance

/openbmc/qemu/tcg/tci/
H A Dtcg-target.h62 #define TCG_TARGET_HAS_eqv_i32 1 macro
/openbmc/qemu/tcg/arm/
H A Dtcg-target.h107 #define TCG_TARGET_HAS_eqv_i32 0 macro
/openbmc/qemu/tcg/sparc64/
H A Dtcg-target.h97 #define TCG_TARGET_HAS_eqv_i32 0 macro
/openbmc/qemu/tcg/mips/
H A Dtcg-target.h124 #define TCG_TARGET_HAS_eqv_i32 0 macro
/openbmc/qemu/tcg/loongarch64/
H A Dtcg-target.h124 #define TCG_TARGET_HAS_eqv_i32 0 macro
/openbmc/qemu/tcg/aarch64/
H A Dtcg-target.h81 #define TCG_TARGET_HAS_eqv_i32 1 macro
/openbmc/qemu/tcg/ppc/
H A Dtcg-target.h88 #define TCG_TARGET_HAS_eqv_i32 1 macro
/openbmc/qemu/tcg/s390x/
H A Dtcg-target.h87 #define TCG_TARGET_HAS_eqv_i32 HAVE_FACILITY(MISC_INSN_EXT3) macro
/openbmc/qemu/tcg/riscv/
H A Dtcg-target.h96 #define TCG_TARGET_HAS_eqv_i32 (cpuinfo & CPUINFO_ZBB) macro
/openbmc/qemu/tcg/i386/
H A Dtcg-target.h141 #define TCG_TARGET_HAS_eqv_i32 0 macro
/openbmc/qemu/include/tcg/
H A Dtcg-opc.h106 DEF(eqv_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_eqv_i32))
/openbmc/qemu/tcg/
H A Dtci.c570 #if TCG_TARGET_HAS_eqv_i32 || TCG_TARGET_HAS_eqv_i64 in tcg_qemu_tb_exec()
H A Dtcg-op.c668 if (TCG_TARGET_HAS_eqv_i32) { in tcg_gen_eqv_i32()
H A Dtcg.c2048 return TCG_TARGET_HAS_eqv_i32; in tcg_op_supported()