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Searched refs:TCG_TARGET_HAS_deposit_i32 (Results 1 – 14 of 14) sorted by relevance

/openbmc/qemu/tcg/tci/
H A Dtcg-target.h58 #define TCG_TARGET_HAS_deposit_i32 1 macro
/openbmc/qemu/tcg/arm/
H A Dtcg-target.h113 #define TCG_TARGET_HAS_deposit_i32 use_armv7_instructions macro
/openbmc/qemu/tcg/sparc64/
H A Dtcg-target.h103 #define TCG_TARGET_HAS_deposit_i32 0 macro
/openbmc/qemu/tcg/mips/
H A Dtcg-target.h158 #define TCG_TARGET_HAS_deposit_i32 use_mips32r2_instructions macro
/openbmc/qemu/tcg/loongarch64/
H A Dtcg-target.h105 #define TCG_TARGET_HAS_deposit_i32 1 macro
/openbmc/qemu/tcg/aarch64/
H A Dtcg-target.h87 #define TCG_TARGET_HAS_deposit_i32 1 macro
/openbmc/qemu/tcg/ppc/
H A Dtcg-target.h94 #define TCG_TARGET_HAS_deposit_i32 1 macro
/openbmc/qemu/tcg/s390x/
H A Dtcg-target.h93 #define TCG_TARGET_HAS_deposit_i32 1 macro
/openbmc/qemu/tcg/riscv/
H A Dtcg-target.h77 #define TCG_TARGET_HAS_deposit_i32 0 macro
/openbmc/qemu/tcg/i386/
H A Dtcg-target.h147 #define TCG_TARGET_HAS_deposit_i32 1 macro
/openbmc/qemu/include/tcg/
H A Dtcg-opc.h79 DEF(deposit_i32, 1, 2, 2, IMPL(TCG_TARGET_HAS_deposit_i32))
/openbmc/qemu/tcg/
H A Dtci.c652 #if TCG_TARGET_HAS_deposit_i32 in tcg_qemu_tb_exec()
H A Dtcg-op.c896 if (TCG_TARGET_HAS_deposit_i32 && TCG_TARGET_deposit_i32_valid(ofs, len)) { in tcg_gen_deposit_i32()
941 } else if (TCG_TARGET_HAS_deposit_i32 in tcg_gen_deposit_z_i32()
H A Dtcg.c2010 return TCG_TARGET_HAS_deposit_i32; in tcg_op_supported()