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Searched refs:TARGET_QS (Results 1 – 4 of 4) sorted by relevance

/openbmc/linux/drivers/net/ethernet/microchip/lan966x/
H A Dlan966x_regs.h24 TARGET_QS = 42, enumerator
1188 #define QS_XTR_GRP_CFG(r) __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 0, r, 2, 4)
1203 #define QS_XTR_RD(r) __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 8, r, 2, 4)
1206 #define QS_XTR_FLUSH __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 24, 0, 1, 4)
1209 #define QS_XTR_DATA_PRESENT __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 28, 0, 1, 4)
1212 #define QS_INJ_GRP_CFG(r) __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 0, r, 2, 4)
1227 #define QS_INJ_WR(r) __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 8, r, 2, 4)
1230 #define QS_INJ_CTRL(r) __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 16, r, 2, 4)
1257 #define QS_INJ_STATUS __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 24, 0, 1, 4)
H A Dlan966x_main.c46 { TARGET_QS, 0x8000, 1 }, /* 0xe2008000 */
/openbmc/linux/drivers/net/ethernet/microchip/sparx5/
H A Dsparx5_main_regs.h47 TARGET_QS = 177, enumerator
6237 #define QS_XTR_GRP_CFG(r) __REG(TARGET_QS,\
6259 #define QS_XTR_RD(r) __REG(TARGET_QS,\
6263 #define QS_XTR_FLUSH __REG(TARGET_QS,\
6273 #define QS_XTR_DATA_PRESENT __REG(TARGET_QS,\
6283 #define QS_INJ_GRP_CFG(r) __REG(TARGET_QS,\
6299 #define QS_INJ_WR(r) __REG(TARGET_QS,\
6303 #define QS_INJ_CTRL(r) __REG(TARGET_QS,\
6337 #define QS_INJ_STATUS __REG(TARGET_QS,\
H A Dsparx5_main.c193 { TARGET_QS, 0x11030000, 2 }, /* 0x611030000 */