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Searched refs:T1 (Results 1 – 21 of 21) sorted by relevance

/openbmc/qemu/include/exec/
H A Dhelper-info.c.inc25 #define DEF_HELPER_FLAGS_1(NAME, FLAGS, RET, T1) \
29 .typemask = dh_typemask(RET, 0) | dh_typemask(T1, 1) \
32 #define DEF_HELPER_FLAGS_2(NAME, FLAGS, RET, T1, T2) \
36 .typemask = dh_typemask(RET, 0) | dh_typemask(T1, 1) \
40 #define DEF_HELPER_FLAGS_3(NAME, FLAGS, RET, T1, T2, T3) \
44 .typemask = dh_typemask(RET, 0) | dh_typemask(T1, 1) \
48 #define DEF_HELPER_FLAGS_4(NAME, FLAGS, RET, T1, T2, T3, T4) \
52 .typemask = dh_typemask(RET, 0) | dh_typemask(T1, 1) \
57 #define DEF_HELPER_FLAGS_5(NAME, FLAGS, RET, T1, T2, T3, T4, T5) \
61 .typemask = dh_typemask(RET, 0) | dh_typemask(T1, 1) \
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/openbmc/qemu/docs/system/
H A Dtarget-sparc64.rst7 (UltraSPARC PC-like machine), Sun4v (T1 PC-like machine), or generic
8 Niagara (T1) machine. The Sun4u emulator is mostly complete, being able
12 The Niagara T1 emulator makes use of firmware and OS binaries supplied
13 in the S10image/ directory of the OpenSPARC T1 project
/openbmc/qemu/target/i386/tcg/
H A Demit.c.inc400 decode->cc_src = s->T1;
407 gen_compute_eflags_c(s, s->T1);
414 decode->cc_src = s->T1;
1143 gen_helper_aad(s->T0, s->T0, s->T1);
1152 gen_helper_aam(s->T0, s->T0, s->T1);
1180 gen_compute_eflags_c(s, s->T1);
1188 tcg_gen_add_tl(s->T0, c_in, s->T1);
1192 tcg_gen_add_tl(s->T0, s->T0, s->T1);
1241 tcg_gen_ext32u_tl(s->T1, s->T1);
1242 tcg_gen_add_i64(s->T0, s->T0, s->T1);
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H A Dtranslate.c135 TCGv T1; member
1281 gen_op_ld_v(s, ot, s->T1, s->A0); in gen_scas()
1282 tcg_gen_mov_tl(cpu_cc_src, s->T1); in gen_scas()
1284 tcg_gen_sub_tl(cpu_cc_dst, s->T0, s->T1); in gen_scas()
1293 gen_op_ld_v(s, ot, s->T1, s->A0); in gen_cmps()
1296 tcg_gen_mov_tl(cpu_cc_src, s->T1); in gen_cmps()
1298 tcg_gen_sub_tl(cpu_cc_dst, s->T0, s->T1); in gen_cmps()
1600 tcg_gen_deposit_tl(tmp, s->T0, s->T1, 16, 16); in gen_shiftd_rm_T1()
1601 tcg_gen_mov_tl(s->T1, s->T0); in gen_shiftd_rm_T1()
1604 tcg_gen_deposit_tl(s->T1, s->T0, s->T1, 16, 16); in gen_shiftd_rm_T1()
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H A Ddecode-new.c.inc211 * and s->T1.
2858 gen_load(s, &decode, 2, s->T1);
2867 gen_load(s, &decode, 2, s->T1);
/openbmc/u-boot/fs/zfs/
H A Dzfs_sha256.c79 uint32_t a, b, c, d, e, f, g, h, t, T1, T2, W[64]; in SHA256Transform() local
92 T1 = h + SIGMA1(e) + Ch(e, f, g) + SHA256_K[t] + W[t]; in SHA256Transform()
94 h = g; g = f; f = e; e = d + T1; in SHA256Transform()
95 d = c; c = b; b = a; a = T1 + T2; in SHA256Transform()
/openbmc/qemu/target/riscv/
H A Dvector_internals.h182 #define OPIVV2(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \ argument
185 TX1 s1 = *((T1 *)vs1 + HS1(i)); \
210 #define OPIVX2(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \ argument
214 *((TD *)vd + HD(i)) = OP(s2, (TX1)(T1)s1); \
H A Dvcrypto_helper.c514 uint64_t T1 = h + sum1_64(e) + ch(e, f, g) + W0; in vsha2c_64() local
520 e = d + T1; in vsha2c_64()
524 a = T1 + T2; in vsha2c_64()
526 T1 = h + sum1_64(e) + ch(e, f, g) + W1; in vsha2c_64()
531 e = d + T1; in vsha2c_64()
535 a = T1 + T2; in vsha2c_64()
548 uint32_t T1 = h + sum1_32(e) + ch(e, f, g) + W0; in vsha2c_32() local
554 e = d + T1; in vsha2c_32()
558 a = T1 + T2; in vsha2c_32()
560 T1 = h + sum1_32(e) + ch(e, f, g) + W1; in vsha2c_32()
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/openbmc/sdbusplus/include/sdbusplus/message/
H A Dread.hpp310 template <typename T, typename T1, typename... Args1>
313 constexpr auto dbusType = utility::tuple_to_array(types::type_id<T1>()); in read()
352 if constexpr (std::is_enum_v<Td<T1>> || in read()
353 std::is_same_v<std::string, Td<T1>>) in read()
370 std::remove_reference_t<T1> t1; in read()
H A Dtypes.hpp240 template <typename T1, typename T2>
241 struct type_id<std::pair<T1, T2>>
245 type_id_v<type_id_downcast_t<T1>>, type_id_v<type_id_downcast_t<T2>>,
H A Dappend.hpp264 template <typename T1, typename T2>
265 struct append_single<std::pair<T1, T2>>
271 std::tuple_cat(types::type_id_nonull<T1>(), types::type_id<T2>())); in op()
/openbmc/openbmc/poky/bitbake/lib/prserv/
H A Ddb.py225 …WHERE T1.version=T2.version AND T1.pkgarch=T2.pkgarch AND T1.value=T2.maxvalue " % (self.table, se…
/openbmc/openbmc-build-scripts/config/
H A D.gitlint101 # ignore=T1,body-min-length
110 # ignore=T1,body-min-length
123 # ignore=T1,body-min-length
/openbmc/qemu/target/loongarch/tcg/
H A Dvec_helper.c1352 #define SSRLNS(NAME, T1, T2, T3) \ argument
1353 static T1 do_ssrlns_ ## NAME(T2 e2, int sa, int sh) \
1355 T1 shft_res; \
1359 shft_res = (((T1)e2) >> sa); \
1398 #define SSRANS(E, T1, T2) \ argument
1399 static T1 do_ssrans_ ## E(T1 e2, int sa, int sh) \
1401 T1 shft_res; \
1446 #define SSRLNU(E, T1, T2, T3) \ argument
1447 static T1 do_ssrlnu_ ## E(T3 e2, int sa, int sh) \
1449 T1 shft_res; \
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/openbmc/u-boot/doc/device-tree-bindings/video/
H A Dintel-gma.txt18 - intel,panel-power-up-delay : T1+T2 time sequence
/openbmc/openbmc/meta-facebook/meta-yosemite4/recipes-phosphor/fans/phosphor-pid-control/
H A Dmonitor-pldm-sensor125 T1)
/openbmc/u-boot/doc/
H A DREADME.bus_vcxk16 EB+CPU5282-T1 | MCF5282 | BuS Elektronik GmbH & Co. KG
/openbmc/ipmitool/src/plugins/lan/
H A Dmd5.c65 #define T1 /* 0xd76aa478 */ (T_MASK ^ 0x28955b87) macro
207 SET(a, b, c, d, 0, 7, T1); in md5_process()
/openbmc/qemu/target/arm/tcg/
H A Dt32.decode465 PLD 1111 1000 1001 ---- 1111 ------------ # (immediate T1)
485 PLDW 1111 1000 1011 ---- 1111 ------------ # (immediate T1)
513 PLI 1111 1001 1001 ---- 1111 ------------ # (immediate T1)
H A Dmve.decode633 # VSHLL T1 encoding; the T2 VSHLL encoding is elsewhere in this file
699 # encodings T1, T2, T3 and the fc bits. These include VPT, which is
/openbmc/u-boot/drivers/power/pmic/
H A DKconfig222 The MC34VR500 is used in conjunction with the FSL T1 and LS1 series