Searched refs:SW_RST (Results 1 – 9 of 9) sorted by relevance
| /openbmc/linux/drivers/thermal/qcom/ |
| H A D | tsens-8960.c | 25 #define SW_RST BIT(1) macro
86 ret = regmap_update_bits(map, CNTL_ADDR, SW_RST, SW_RST); in resume_8960()
136 ret = regmap_write(priv->tm_map, CNTL_ADDR, reg | SW_RST); in enable_8960()
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| /openbmc/linux/drivers/clk/imx/ |
| H A D | clk-composite-7ulp.c | 25 #define SW_RST BIT(28) macro
44 val |= SW_RST; in pcc_gate_enable()
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| /openbmc/u-boot/drivers/net/phy/ |
| H A D | b53.c | 84 #define SW_RST BIT(7) macro
413 reg |= SW_RST | EN_SW_RST | EN_CH_RST; in b53_switch_reset()
418 if (!(reg & SW_RST)) in b53_switch_reset()
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| /openbmc/linux/drivers/net/ethernet/moxa/ |
| H A D | moxart_ether.h | 185 #define SW_RST BIT(2) /* software reset, last 64 AHB clocks */ macro
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| H A D | moxart_ether.c | 93 writel(SW_RST, priv->base + REG_MAC_CTRL); in moxart_mac_reset()
94 while (readl(priv->base + REG_MAC_CTRL) & SW_RST) in moxart_mac_reset()
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| /openbmc/linux/drivers/net/dsa/b53/ |
| H A D | b53_regs.h | 150 #define SW_RST BIT(7) macro
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| H A D | b53_common.c | 828 reg |= SW_RST | EN_SW_RST | EN_CH_RST; in b53_switch_reset()
833 if (!(reg & SW_RST)) in b53_switch_reset()
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| /openbmc/qemu/hw/ssi/ |
| H A D | ibex_spi_host.c | 52 FIELD(CONTROL, SW_RST, 30, 1)
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| /openbmc/linux/drivers/spi/ |
| H A D | spi-mtk-snfi.c | 189 #define SW_RST BIT(28) macro
418 nfi_rmw32(snf, SNF_MISC_CTL, 0, SW_RST); in mtk_snand_mac_reset()
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