Searched refs:SUNXI_DRAM_PHY0_BASE (Results 1 – 7 of 7) sorted by relevance
33 #define SUNXI_DRAM_PHY0_BASE 0x04005000 macro
47 #define SUNXI_DRAM_PHY0_BASE (REGS_AHB0_BASE + 0x65000) macro
158 #define SUNXI_DRAM_PHY0_BASE 0x01c65000 macro
81 (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE; in mctl_phy_pir_init()184 (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE; in mctl_set_timing_lpddr3()423 (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE; in mctl_com_init()471 (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE; in mctl_bit_delay_set()531 (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE; in mctl_channel_init()
56 mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE; in mctl_dll_init()111 mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE; in mctl_channel_init()
99 (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE; in mctl_init()
453 mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE; in mctl_channel_init()