1 /*
2 * QEMU IDE Emulation: microdrive (CF / PCMCIA)
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2006 Openedhand Ltd.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25
26 #include "qemu/osdep.h"
27 #include "hw/pcmcia.h"
28 #include "migration/vmstate.h"
29 #include "qapi/error.h"
30 #include "qemu/module.h"
31 #include "sysemu/dma.h"
32 #include "hw/irq.h"
33
34 #include "qom/object.h"
35 #include "ide-internal.h"
36
37 #define TYPE_MICRODRIVE "microdrive"
38 OBJECT_DECLARE_SIMPLE_TYPE(MicroDriveState, MICRODRIVE)
39
40 /***********************************************************/
41 /* CF-ATA Microdrive */
42
43 #define METADATA_SIZE 0x20
44
45 /* DSCM-1XXXX Microdrive hard disk with CF+ II / PCMCIA interface. */
46
47 struct MicroDriveState {
48 /*< private >*/
49 PCMCIACardState parent_obj;
50 /*< public >*/
51
52 IDEBus bus;
53 uint32_t attr_base;
54 uint32_t io_base;
55
56 /* Card state */
57 uint8_t opt;
58 uint8_t stat;
59 uint8_t pins;
60
61 uint8_t ctrl;
62 uint16_t io;
63 uint8_t cycle;
64 };
65
66 /* Register bitfields */
67 enum md_opt {
68 OPT_MODE_MMAP = 0,
69 OPT_MODE_IOMAP16 = 1,
70 OPT_MODE_IOMAP1 = 2,
71 OPT_MODE_IOMAP2 = 3,
72 OPT_MODE = 0x3f,
73 OPT_LEVIREQ = 0x40,
74 OPT_SRESET = 0x80,
75 };
76 enum md_cstat {
77 STAT_INT = 0x02,
78 STAT_PWRDWN = 0x04,
79 STAT_XE = 0x10,
80 STAT_IOIS8 = 0x20,
81 STAT_SIGCHG = 0x40,
82 STAT_CHANGED = 0x80,
83 };
84 enum md_pins {
85 PINS_MRDY = 0x02,
86 PINS_CRDY = 0x20,
87 };
88 enum md_ctrl {
89 CTRL_IEN = 0x02,
90 CTRL_SRST = 0x04,
91 };
92
md_interrupt_update(MicroDriveState * s)93 static inline void md_interrupt_update(MicroDriveState *s)
94 {
95 PCMCIACardState *card = PCMCIA_CARD(s);
96
97 if (card->slot == NULL) {
98 return;
99 }
100
101 qemu_set_irq(card->slot->irq,
102 !(s->stat & STAT_INT) && /* Inverted */
103 !(s->ctrl & (CTRL_IEN | CTRL_SRST)) &&
104 !(s->opt & OPT_SRESET));
105 }
106
md_set_irq(void * opaque,int irq,int level)107 static void md_set_irq(void *opaque, int irq, int level)
108 {
109 MicroDriveState *s = opaque;
110
111 if (level) {
112 s->stat |= STAT_INT;
113 } else {
114 s->stat &= ~STAT_INT;
115 }
116
117 md_interrupt_update(s);
118 }
119
md_reset(DeviceState * dev)120 static void md_reset(DeviceState *dev)
121 {
122 MicroDriveState *s = MICRODRIVE(dev);
123
124 s->opt = OPT_MODE_MMAP;
125 s->stat = 0;
126 s->pins = 0;
127 s->cycle = 0;
128 s->ctrl = 0;
129 ide_bus_reset(&s->bus);
130 }
131
md_attr_read(PCMCIACardState * card,uint32_t at)132 static uint8_t md_attr_read(PCMCIACardState *card, uint32_t at)
133 {
134 MicroDriveState *s = MICRODRIVE(card);
135 PCMCIACardClass *pcc = PCMCIA_CARD_GET_CLASS(card);
136
137 if (at < s->attr_base) {
138 if (at < pcc->cis_len) {
139 return pcc->cis[at];
140 } else {
141 return 0x00;
142 }
143 }
144
145 at -= s->attr_base;
146
147 switch (at) {
148 case 0x00: /* Configuration Option Register */
149 return s->opt;
150 case 0x02: /* Card Configuration Status Register */
151 if (s->ctrl & CTRL_IEN) {
152 return s->stat & ~STAT_INT;
153 } else {
154 return s->stat;
155 }
156 case 0x04: /* Pin Replacement Register */
157 return (s->pins & PINS_CRDY) | 0x0c;
158 case 0x06: /* Socket and Copy Register */
159 return 0x00;
160 #ifdef VERBOSE
161 default:
162 printf("%s: Bad attribute space register %02x\n", __func__, at);
163 #endif
164 }
165
166 return 0;
167 }
168
md_attr_write(PCMCIACardState * card,uint32_t at,uint8_t value)169 static void md_attr_write(PCMCIACardState *card, uint32_t at, uint8_t value)
170 {
171 MicroDriveState *s = MICRODRIVE(card);
172
173 at -= s->attr_base;
174
175 switch (at) {
176 case 0x00: /* Configuration Option Register */
177 s->opt = value & 0xcf;
178 if (value & OPT_SRESET) {
179 device_cold_reset(DEVICE(s));
180 }
181 md_interrupt_update(s);
182 break;
183 case 0x02: /* Card Configuration Status Register */
184 if ((s->stat ^ value) & STAT_PWRDWN) {
185 s->pins |= PINS_CRDY;
186 }
187 s->stat &= 0x82;
188 s->stat |= value & 0x74;
189 md_interrupt_update(s);
190 /* Word 170 in Identify Device must be equal to STAT_XE */
191 break;
192 case 0x04: /* Pin Replacement Register */
193 s->pins &= PINS_CRDY;
194 s->pins |= value & PINS_MRDY;
195 break;
196 case 0x06: /* Socket and Copy Register */
197 break;
198 default:
199 printf("%s: Bad attribute space register %02x\n", __func__, at);
200 }
201 }
202
md_common_read(PCMCIACardState * card,uint32_t at)203 static uint16_t md_common_read(PCMCIACardState *card, uint32_t at)
204 {
205 MicroDriveState *s = MICRODRIVE(card);
206 IDEState *ifs;
207 uint16_t ret;
208 at -= s->io_base;
209
210 switch (s->opt & OPT_MODE) {
211 case OPT_MODE_MMAP:
212 if ((at & ~0x3ff) == 0x400) {
213 at = 0;
214 }
215 break;
216 case OPT_MODE_IOMAP16:
217 at &= 0xf;
218 break;
219 case OPT_MODE_IOMAP1:
220 if ((at & ~0xf) == 0x3f0) {
221 at -= 0x3e8;
222 } else if ((at & ~0xf) == 0x1f0) {
223 at -= 0x1f0;
224 }
225 break;
226 case OPT_MODE_IOMAP2:
227 if ((at & ~0xf) == 0x370) {
228 at -= 0x368;
229 } else if ((at & ~0xf) == 0x170) {
230 at -= 0x170;
231 }
232 }
233
234 switch (at) {
235 case 0x0: /* Even RD Data */
236 case 0x8:
237 return ide_data_readw(&s->bus, 0);
238
239 /* TODO: 8-bit accesses */
240 if (s->cycle) {
241 ret = s->io >> 8;
242 } else {
243 s->io = ide_data_readw(&s->bus, 0);
244 ret = s->io & 0xff;
245 }
246 s->cycle = !s->cycle;
247 return ret;
248 case 0x9: /* Odd RD Data */
249 return s->io >> 8;
250 case 0xd: /* Error */
251 return ide_ioport_read(&s->bus, 0x1);
252 case 0xe: /* Alternate Status */
253 ifs = ide_bus_active_if(&s->bus);
254 if (ifs->blk) {
255 return ifs->status;
256 } else {
257 return 0;
258 }
259 case 0xf: /* Device Address */
260 ifs = ide_bus_active_if(&s->bus);
261 return 0xc2 | ((~ifs->select << 2) & 0x3c);
262 default:
263 return ide_ioport_read(&s->bus, at);
264 }
265
266 return 0;
267 }
268
md_common_write(PCMCIACardState * card,uint32_t at,uint16_t value)269 static void md_common_write(PCMCIACardState *card, uint32_t at, uint16_t value)
270 {
271 MicroDriveState *s = MICRODRIVE(card);
272 at -= s->io_base;
273
274 switch (s->opt & OPT_MODE) {
275 case OPT_MODE_MMAP:
276 if ((at & ~0x3ff) == 0x400) {
277 at = 0;
278 }
279 break;
280 case OPT_MODE_IOMAP16:
281 at &= 0xf;
282 break;
283 case OPT_MODE_IOMAP1:
284 if ((at & ~0xf) == 0x3f0) {
285 at -= 0x3e8;
286 } else if ((at & ~0xf) == 0x1f0) {
287 at -= 0x1f0;
288 }
289 break;
290 case OPT_MODE_IOMAP2:
291 if ((at & ~0xf) == 0x370) {
292 at -= 0x368;
293 } else if ((at & ~0xf) == 0x170) {
294 at -= 0x170;
295 }
296 }
297
298 switch (at) {
299 case 0x0: /* Even WR Data */
300 case 0x8:
301 ide_data_writew(&s->bus, 0, value);
302 break;
303
304 /* TODO: 8-bit accesses */
305 if (s->cycle) {
306 ide_data_writew(&s->bus, 0, s->io | (value << 8));
307 } else {
308 s->io = value & 0xff;
309 }
310 s->cycle = !s->cycle;
311 break;
312 case 0x9:
313 s->io = value & 0xff;
314 s->cycle = !s->cycle;
315 break;
316 case 0xd: /* Features */
317 ide_ioport_write(&s->bus, 0x1, value);
318 break;
319 case 0xe: /* Device Control */
320 s->ctrl = value;
321 if (value & CTRL_SRST) {
322 device_cold_reset(DEVICE(s));
323 }
324 md_interrupt_update(s);
325 break;
326 default:
327 if (s->stat & STAT_PWRDWN) {
328 s->pins |= PINS_CRDY;
329 s->stat &= ~STAT_PWRDWN;
330 }
331 ide_ioport_write(&s->bus, at, value);
332 }
333 }
334
335 static const VMStateDescription vmstate_microdrive = {
336 .name = "microdrive",
337 .version_id = 3,
338 .minimum_version_id = 0,
339 .fields = (const VMStateField[]) {
340 VMSTATE_UINT8(opt, MicroDriveState),
341 VMSTATE_UINT8(stat, MicroDriveState),
342 VMSTATE_UINT8(pins, MicroDriveState),
343 VMSTATE_UINT8(ctrl, MicroDriveState),
344 VMSTATE_UINT16(io, MicroDriveState),
345 VMSTATE_UINT8(cycle, MicroDriveState),
346 VMSTATE_IDE_BUS(bus, MicroDriveState),
347 VMSTATE_IDE_DRIVES(bus.ifs, MicroDriveState),
348 VMSTATE_END_OF_LIST()
349 }
350 };
351
352 static const uint8_t dscm1xxxx_cis[0x14a] = {
353 [0x000] = CISTPL_DEVICE, /* 5V Device Information */
354 [0x002] = 0x03, /* Tuple length = 4 bytes */
355 [0x004] = 0xdb, /* ID: DTYPE_FUNCSPEC, non WP, DSPEED_150NS */
356 [0x006] = 0x01, /* Size = 2K bytes */
357 [0x008] = CISTPL_ENDMARK,
358
359 [0x00a] = CISTPL_DEVICE_OC, /* Additional Device Information */
360 [0x00c] = 0x04, /* Tuple length = 4 byest */
361 [0x00e] = 0x03, /* Conditions: Ext = 0, Vcc 3.3V, MWAIT = 1 */
362 [0x010] = 0xdb, /* ID: DTYPE_FUNCSPEC, non WP, DSPEED_150NS */
363 [0x012] = 0x01, /* Size = 2K bytes */
364 [0x014] = CISTPL_ENDMARK,
365
366 [0x016] = CISTPL_JEDEC_C, /* JEDEC ID */
367 [0x018] = 0x02, /* Tuple length = 2 bytes */
368 [0x01a] = 0xdf, /* PC Card ATA with no Vpp required */
369 [0x01c] = 0x01,
370
371 [0x01e] = CISTPL_MANFID, /* Manufacture ID */
372 [0x020] = 0x04, /* Tuple length = 4 bytes */
373 [0x022] = 0xa4, /* TPLMID_MANF = 00a4 (IBM) */
374 [0x024] = 0x00,
375 [0x026] = 0x00, /* PLMID_CARD = 0000 */
376 [0x028] = 0x00,
377
378 [0x02a] = CISTPL_VERS_1, /* Level 1 Version */
379 [0x02c] = 0x12, /* Tuple length = 23 bytes */
380 [0x02e] = 0x04, /* Major Version = JEIDA 4.2 / PCMCIA 2.1 */
381 [0x030] = 0x01, /* Minor Version = 1 */
382 [0x032] = 'I',
383 [0x034] = 'B',
384 [0x036] = 'M',
385 [0x038] = 0x00,
386 [0x03a] = 'm',
387 [0x03c] = 'i',
388 [0x03e] = 'c',
389 [0x040] = 'r',
390 [0x042] = 'o',
391 [0x044] = 'd',
392 [0x046] = 'r',
393 [0x048] = 'i',
394 [0x04a] = 'v',
395 [0x04c] = 'e',
396 [0x04e] = 0x00,
397 [0x050] = CISTPL_ENDMARK,
398
399 [0x052] = CISTPL_FUNCID, /* Function ID */
400 [0x054] = 0x02, /* Tuple length = 2 bytes */
401 [0x056] = 0x04, /* TPLFID_FUNCTION = Fixed Disk */
402 [0x058] = 0x01, /* TPLFID_SYSINIT: POST = 1, ROM = 0 */
403
404 [0x05a] = CISTPL_FUNCE, /* Function Extension */
405 [0x05c] = 0x02, /* Tuple length = 2 bytes */
406 [0x05e] = 0x01, /* TPLFE_TYPE = Disk Device Interface */
407 [0x060] = 0x01, /* TPLFE_DATA = PC Card ATA Interface */
408
409 [0x062] = CISTPL_FUNCE, /* Function Extension */
410 [0x064] = 0x03, /* Tuple length = 3 bytes */
411 [0x066] = 0x02, /* TPLFE_TYPE = Basic PC Card ATA Interface */
412 [0x068] = 0x08, /* TPLFE_DATA: Rotating, Unique, Single */
413 [0x06a] = 0x0f, /* TPLFE_DATA: Sleep, Standby, Idle, Auto */
414
415 [0x06c] = CISTPL_CONFIG, /* Configuration */
416 [0x06e] = 0x05, /* Tuple length = 5 bytes */
417 [0x070] = 0x01, /* TPCC_RASZ = 2 bytes, TPCC_RMSZ = 1 byte */
418 [0x072] = 0x07, /* TPCC_LAST = 7 */
419 [0x074] = 0x00, /* TPCC_RADR = 0200 */
420 [0x076] = 0x02,
421 [0x078] = 0x0f, /* TPCC_RMSK = 200, 202, 204, 206 */
422
423 [0x07a] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
424 [0x07c] = 0x0b, /* Tuple length = 11 bytes */
425 [0x07e] = 0xc0, /* TPCE_INDX = Memory Mode, Default, Iface */
426 [0x080] = 0xc0, /* TPCE_IF = Memory, no BVDs, no WP, READY */
427 [0x082] = 0xa1, /* TPCE_FS = Vcc only, no I/O, Memory, Misc */
428 [0x084] = 0x27, /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
429 [0x086] = 0x55, /* NomV: 5.0 V */
430 [0x088] = 0x4d, /* MinV: 4.5 V */
431 [0x08a] = 0x5d, /* MaxV: 5.5 V */
432 [0x08c] = 0x4e, /* Peakl: 450 mA */
433 [0x08e] = 0x08, /* TPCE_MS = 1 window, 1 byte, Host address */
434 [0x090] = 0x00, /* Window descriptor: Window length = 0 */
435 [0x092] = 0x20, /* TPCE_MI: support power down mode, RW */
436
437 [0x094] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
438 [0x096] = 0x06, /* Tuple length = 6 bytes */
439 [0x098] = 0x00, /* TPCE_INDX = Memory Mode, no Default */
440 [0x09a] = 0x01, /* TPCE_FS = Vcc only, no I/O, no Memory */
441 [0x09c] = 0x21, /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
442 [0x09e] = 0xb5, /* NomV: 3.3 V */
443 [0x0a0] = 0x1e,
444 [0x0a2] = 0x3e, /* Peakl: 350 mA */
445
446 [0x0a4] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
447 [0x0a6] = 0x0d, /* Tuple length = 13 bytes */
448 [0x0a8] = 0xc1, /* TPCE_INDX = I/O and Memory Mode, Default */
449 [0x0aa] = 0x41, /* TPCE_IF = I/O and Memory, no BVD, no WP */
450 [0x0ac] = 0x99, /* TPCE_FS = Vcc only, I/O, Interrupt, Misc */
451 [0x0ae] = 0x27, /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
452 [0x0b0] = 0x55, /* NomV: 5.0 V */
453 [0x0b2] = 0x4d, /* MinV: 4.5 V */
454 [0x0b4] = 0x5d, /* MaxV: 5.5 V */
455 [0x0b6] = 0x4e, /* Peakl: 450 mA */
456 [0x0b8] = 0x64, /* TPCE_IO = 16-byte boundary, 16/8 accesses */
457 [0x0ba] = 0xf0, /* TPCE_IR = MASK, Level, Pulse, Share */
458 [0x0bc] = 0xff, /* IRQ0..IRQ7 supported */
459 [0x0be] = 0xff, /* IRQ8..IRQ15 supported */
460 [0x0c0] = 0x20, /* TPCE_MI = support power down mode */
461
462 [0x0c2] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
463 [0x0c4] = 0x06, /* Tuple length = 6 bytes */
464 [0x0c6] = 0x01, /* TPCE_INDX = I/O and Memory Mode */
465 [0x0c8] = 0x01, /* TPCE_FS = Vcc only, no I/O, no Memory */
466 [0x0ca] = 0x21, /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
467 [0x0cc] = 0xb5, /* NomV: 3.3 V */
468 [0x0ce] = 0x1e,
469 [0x0d0] = 0x3e, /* Peakl: 350 mA */
470
471 [0x0d2] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
472 [0x0d4] = 0x12, /* Tuple length = 18 bytes */
473 [0x0d6] = 0xc2, /* TPCE_INDX = I/O Primary Mode */
474 [0x0d8] = 0x41, /* TPCE_IF = I/O and Memory, no BVD, no WP */
475 [0x0da] = 0x99, /* TPCE_FS = Vcc only, I/O, Interrupt, Misc */
476 [0x0dc] = 0x27, /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
477 [0x0de] = 0x55, /* NomV: 5.0 V */
478 [0x0e0] = 0x4d, /* MinV: 4.5 V */
479 [0x0e2] = 0x5d, /* MaxV: 5.5 V */
480 [0x0e4] = 0x4e, /* Peakl: 450 mA */
481 [0x0e6] = 0xea, /* TPCE_IO = 1K boundary, 16/8 access, Range */
482 [0x0e8] = 0x61, /* Range: 2 fields, 2 bytes addr, 1 byte len */
483 [0x0ea] = 0xf0, /* Field 1 address = 0x01f0 */
484 [0x0ec] = 0x01,
485 [0x0ee] = 0x07, /* Address block length = 8 */
486 [0x0f0] = 0xf6, /* Field 2 address = 0x03f6 */
487 [0x0f2] = 0x03,
488 [0x0f4] = 0x01, /* Address block length = 2 */
489 [0x0f6] = 0xee, /* TPCE_IR = IRQ E, Level, Pulse, Share */
490 [0x0f8] = 0x20, /* TPCE_MI = support power down mode */
491
492 [0x0fa] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
493 [0x0fc] = 0x06, /* Tuple length = 6 bytes */
494 [0x0fe] = 0x02, /* TPCE_INDX = I/O Primary Mode, no Default */
495 [0x100] = 0x01, /* TPCE_FS = Vcc only, no I/O, no Memory */
496 [0x102] = 0x21, /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
497 [0x104] = 0xb5, /* NomV: 3.3 V */
498 [0x106] = 0x1e,
499 [0x108] = 0x3e, /* Peakl: 350 mA */
500
501 [0x10a] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
502 [0x10c] = 0x12, /* Tuple length = 18 bytes */
503 [0x10e] = 0xc3, /* TPCE_INDX = I/O Secondary Mode, Default */
504 [0x110] = 0x41, /* TPCE_IF = I/O and Memory, no BVD, no WP */
505 [0x112] = 0x99, /* TPCE_FS = Vcc only, I/O, Interrupt, Misc */
506 [0x114] = 0x27, /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
507 [0x116] = 0x55, /* NomV: 5.0 V */
508 [0x118] = 0x4d, /* MinV: 4.5 V */
509 [0x11a] = 0x5d, /* MaxV: 5.5 V */
510 [0x11c] = 0x4e, /* Peakl: 450 mA */
511 [0x11e] = 0xea, /* TPCE_IO = 1K boundary, 16/8 access, Range */
512 [0x120] = 0x61, /* Range: 2 fields, 2 byte addr, 1 byte len */
513 [0x122] = 0x70, /* Field 1 address = 0x0170 */
514 [0x124] = 0x01,
515 [0x126] = 0x07, /* Address block length = 8 */
516 [0x128] = 0x76, /* Field 2 address = 0x0376 */
517 [0x12a] = 0x03,
518 [0x12c] = 0x01, /* Address block length = 2 */
519 [0x12e] = 0xee, /* TPCE_IR = IRQ E, Level, Pulse, Share */
520 [0x130] = 0x20, /* TPCE_MI = support power down mode */
521
522 [0x132] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
523 [0x134] = 0x06, /* Tuple length = 6 bytes */
524 [0x136] = 0x03, /* TPCE_INDX = I/O Secondary Mode */
525 [0x138] = 0x01, /* TPCE_FS = Vcc only, no I/O, no Memory */
526 [0x13a] = 0x21, /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
527 [0x13c] = 0xb5, /* NomV: 3.3 V */
528 [0x13e] = 0x1e,
529 [0x140] = 0x3e, /* Peakl: 350 mA */
530
531 [0x142] = CISTPL_NO_LINK, /* No Link */
532 [0x144] = 0x00, /* Tuple length = 0 bytes */
533
534 [0x146] = CISTPL_END, /* Tuple End */
535 };
536
537 #define TYPE_DSCM1XXXX "dscm1xxxx"
538
dscm1xxxx_attach(PCMCIACardState * card)539 static int dscm1xxxx_attach(PCMCIACardState *card)
540 {
541 MicroDriveState *md = MICRODRIVE(card);
542 PCMCIACardClass *pcc = PCMCIA_CARD_GET_CLASS(card);
543
544 md->attr_base = pcc->cis[0x74] | (pcc->cis[0x76] << 8);
545 md->io_base = 0x0;
546
547 device_cold_reset(DEVICE(md));
548 md_interrupt_update(md);
549
550 return 0;
551 }
552
dscm1xxxx_detach(PCMCIACardState * card)553 static int dscm1xxxx_detach(PCMCIACardState *card)
554 {
555 MicroDriveState *md = MICRODRIVE(card);
556
557 device_cold_reset(DEVICE(md));
558 return 0;
559 }
560
dscm1xxxx_init(DriveInfo * dinfo)561 PCMCIACardState *dscm1xxxx_init(DriveInfo *dinfo)
562 {
563 MicroDriveState *md;
564
565 md = MICRODRIVE(object_new(TYPE_DSCM1XXXX));
566 qdev_realize(DEVICE(md), NULL, &error_fatal);
567
568 if (dinfo != NULL) {
569 ide_bus_create_drive(&md->bus, 0, dinfo);
570 }
571 md->bus.ifs[0].drive_kind = IDE_CFATA;
572 md->bus.ifs[0].mdata_size = METADATA_SIZE;
573 md->bus.ifs[0].mdata_storage = g_malloc0(METADATA_SIZE);
574
575 return PCMCIA_CARD(md);
576 }
577
dscm1xxxx_class_init(ObjectClass * oc,void * data)578 static void dscm1xxxx_class_init(ObjectClass *oc, void *data)
579 {
580 PCMCIACardClass *pcc = PCMCIA_CARD_CLASS(oc);
581 DeviceClass *dc = DEVICE_CLASS(oc);
582
583 pcc->cis = dscm1xxxx_cis;
584 pcc->cis_len = sizeof(dscm1xxxx_cis);
585
586 pcc->attach = dscm1xxxx_attach;
587 pcc->detach = dscm1xxxx_detach;
588 /* Reason: Needs to be wired-up in code, see dscm1xxxx_init() */
589 dc->user_creatable = false;
590 }
591
592 static const TypeInfo dscm1xxxx_type_info = {
593 .name = TYPE_DSCM1XXXX,
594 .parent = TYPE_MICRODRIVE,
595 .class_init = dscm1xxxx_class_init,
596 };
597
microdrive_realize(DeviceState * dev,Error ** errp)598 static void microdrive_realize(DeviceState *dev, Error **errp)
599 {
600 MicroDriveState *md = MICRODRIVE(dev);
601
602 ide_bus_init_output_irq(&md->bus, qemu_allocate_irq(md_set_irq, md, 0));
603 }
604
microdrive_init(Object * obj)605 static void microdrive_init(Object *obj)
606 {
607 MicroDriveState *md = MICRODRIVE(obj);
608
609 ide_bus_init(&md->bus, sizeof(md->bus), DEVICE(obj), 0, 1);
610 }
611
microdrive_class_init(ObjectClass * oc,void * data)612 static void microdrive_class_init(ObjectClass *oc, void *data)
613 {
614 DeviceClass *dc = DEVICE_CLASS(oc);
615 PCMCIACardClass *pcc = PCMCIA_CARD_CLASS(oc);
616
617 pcc->attr_read = md_attr_read;
618 pcc->attr_write = md_attr_write;
619 pcc->common_read = md_common_read;
620 pcc->common_write = md_common_write;
621 pcc->io_read = md_common_read;
622 pcc->io_write = md_common_write;
623
624 dc->realize = microdrive_realize;
625 dc->reset = md_reset;
626 dc->vmsd = &vmstate_microdrive;
627 }
628
629 static const TypeInfo microdrive_type_info = {
630 .name = TYPE_MICRODRIVE,
631 .parent = TYPE_PCMCIA_CARD,
632 .instance_size = sizeof(MicroDriveState),
633 .instance_init = microdrive_init,
634 .abstract = true,
635 .class_init = microdrive_class_init,
636 };
637
microdrive_register_types(void)638 static void microdrive_register_types(void)
639 {
640 type_register_static(µdrive_type_info);
641 type_register_static(&dscm1xxxx_type_info);
642 }
643
644 type_init(microdrive_register_types)
645