Searched refs:STATE1_ASY_VSYNCPOL_NEGATIVE_TRUE (Results 1 – 2 of 2) sorted by relevance
51 #define STATE1_ASY_VSYNCPOL_NEGATIVE_TRUE (1 << 13) macro
626 reg_val |= STATE1_ASY_VSYNCPOL_NEGATIVE_TRUE; in tegra_dc_sor_config_panel()