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Searched refs:SSP_CTRL1_PHASE (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/arm/include/asm/arch-mxs/
H A Dregs-ssp.h263 #define SSP_CTRL1_PHASE (1 << 10) macro
/openbmc/u-boot/drivers/spi/
H A Dmxs_spi.c99 reg |= (mxs_slave->mode & SPI_CPHA) ? SSP_CTRL1_PHASE : 0; in spi_claim_bus()