| /openbmc/linux/drivers/clk/mxs/ |
| H A D | clk-imx28.c | 28 #define SSP1 (CLKCTRL + 0x00a0) macro
195 clks[ssp1_div] = mxs_clk_div("ssp1_div", "ssp1_sel", SSP1, 0, 9, 29); in mx28_clocks_init()
214 clks[ssp1] = mxs_clk_gate("ssp1", "ssp1_div", SSP1, 31); in mx28_clocks_init()
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| /openbmc/linux/drivers/pinctrl/ |
| H A D | pinctrl-lpc18xx.c | 240 LPC_P(0,0, GPIO, SSP1, ENET, SGPIO, R, R, I2S0_TX_WS,I2S1, 0, ND);
241 LPC_P(0,1, GPIO, SSP1,ENET_ALT,SGPIO, R, R, ENET, I2S1, 0, ND);
245 LPC_P(1,3, GPIO, CTOUT, SGPIO, EMC, USB0, SSP1, R, SDMMC, 0, ND);
246 LPC_P(1,4, GPIO, CTOUT, SGPIO, EMC, USB0, SSP1, R, SDMMC, 0, ND);
247 LPC_P(1,5, GPIO, CTOUT, R, EMC, USB0, SSP1, SGPIO, SDMMC, 0, ND);
261 LPC_P(1,19, ENET, SSP1, R, R, CLKOUT, R, I2S0_RX_MCLK,I2S1, 0, ND);
262 LPC_P(1,20, GPIO, SSP1, R, ENET, TIMER0, R, SGPIO, R, 0, ND);
406 LPC_P(f,4, SSP1, CLKIN, TRACE, R, R, R, I2S0_TX_MCLK,I2S0_RX_SCK, 0, ND);
407 LPC_P(f,5, R, UART3, SSP1, TRACE, GPIO, R, SGPIO, R, ADC1|4, ND);
408 LPC_P(f,6, R, UART3, SSP1, TRACE, GPIO, R, SGPIO, I2S1, ADC1|3, ND);
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/reset/ |
| H A D | nxp,lpc1850-rgu.txt | 51 51 SSP1
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| /openbmc/linux/Documentation/devicetree/bindings/clock/ |
| H A D | lpc1850-cgu.txt | 62 15 BASE_SSP1_CLK Base clock for SSP1
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| /openbmc/linux/Documentation/devicetree/bindings/dma/ |
| H A D | stericsson,dma40.yaml | 31 9: Synchronous Serial Port SSP1
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| /openbmc/linux/drivers/clk/pxa/ |
| H A D | clk-pxa3xx.c | 250 PXA3XX_CKEN_1RATE("pxa3xx-ssp.0", NULL, SSP1, pxa3xx_13MHz_bus_parents),
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| H A D | clk-pxa27x.c | 142 PXA27X_PBUS_CKEN("pxa27x-ssp.0", NULL, SSP1, 1, 24, 0),
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| /openbmc/linux/drivers/clk/nxp/ |
| H A D | clk-lpc18xx-cgu.c | 235 LPC1XX_CGU_BASE_CLK(SSP1, base_common_src_ids, 0),
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| H A D | clk-lpc32xx.c | 249 LPC32XX_CLK_DEFINE(SSP1, "ssp1", 0x0, LPC32XX_CLK_HCLK),
1265 LPC32XX_DEFINE_GATE(SSP1, SSP_CTRL, 1, 0),
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