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Searched refs:SSCG_PLL_OUTPUT_DIV_VAL_MASK (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/arm/mach-imx/imx8m/
H A Dclock.c232 divq = (pll_cfg2 & SSCG_PLL_OUTPUT_DIV_VAL_MASK) >> in decode_sscg_pll()
587 val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK | in dram_pll_init()
599 val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK | in dram_pll_init()
611 val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK | in dram_pll_init()
623 val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK | in dram_pll_init()
/openbmc/u-boot/arch/arm/include/asm/arch-imx8m/
H A Dclock.h577 #define SSCG_PLL_OUTPUT_DIV_VAL_MASK (0x3f << 1) macro
580 SSCG_PLL_OUTPUT_DIV_VAL_MASK)