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Searched refs:SSCG_PLL_FEEDBACK_DIV_F1_MASK (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/arm/mach-imx/imx8m/
H A Dclock.c228 divf1 = (pll_cfg2 & SSCG_PLL_FEEDBACK_DIV_F1_MASK) >> in decode_sscg_pll()
589 SSCG_PLL_FEEDBACK_DIV_F1_MASK | in dram_pll_init()
601 SSCG_PLL_FEEDBACK_DIV_F1_MASK | in dram_pll_init()
613 SSCG_PLL_FEEDBACK_DIV_F1_MASK | in dram_pll_init()
625 SSCG_PLL_FEEDBACK_DIV_F1_MASK | in dram_pll_init()
/openbmc/u-boot/arch/arm/include/asm/arch-imx8m/
H A Dclock.h569 #define SSCG_PLL_FEEDBACK_DIV_F1_MASK (0x3f << 13) macro
572 SSCG_PLL_FEEDBACK_DIV_F1_MASK)