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Searched refs:SSCG_PLL_BYPASS1_MASK (Results 1 – 3 of 3) sorted by relevance

/openbmc/linux/drivers/clk/imx/
H A Dclk-sscg-pll.c65 #define SSCG_PLL_BYPASS1_MASK BIT(5) macro
346 } else if (val & SSCG_PLL_BYPASS1_MASK) { in clk_sscg_pll_recalc_rate()
393 else if (val & SSCG_PLL_BYPASS1_MASK) in clk_sscg_pll_get_parent()
/openbmc/u-boot/arch/arm/mach-imx/imx8m/
H A Dclock.c220 if ((pll_cfg0 & SSCG_PLL_BYPASS1_MASK) || in decode_sscg_pll()
581 setbits_le32(pll_control_reg, SSCG_PLL_BYPASS1_MASK); in dram_pll_init()
643 clrbits_le32(pll_control_reg, SSCG_PLL_BYPASS1_MASK); in dram_pll_init()
/openbmc/u-boot/arch/arm/include/asm/arch-imx8m/
H A Dclock.h548 #define SSCG_PLL_BYPASS1_MASK BIT(5) macro