Searched refs:SR_S (Results 1 – 8 of 8) sorted by relevance
241 #define SR_S 0x2000 macro586 return (env->sr & SR_S) == 0 ? 1 : 0; in cpu_mmu_index()618 if (env->sr & SR_S) { in cpu_get_tb_cpu_state()
206 if (semihosting_enabled((env->sr & SR_S) == 0) in cf_interrupt_all()235 env->sr |= SR_S; in cf_interrupt_all()318 sr |= SR_S; in m68k_interrupt_all()480 if (env->sr & SR_S) { /* SUPERVISOR */ in m68k_cpu_transaction_failed()
465 if (env->sr & SR_S) { in m68k_switch_sp()476 new_sp = (env->sr & SR_S && env->cacr & M68K_CACR_EUSP) in m68k_switch_sp()950 if (env->sr & SR_S) { in m68k_cpu_get_phys_page_debug()
86 cpu_m68k_set_sr(env, SR_S | SR_I); in m68k_cpu_reset_hold()
4352 if (IS_USER(s) || (ext & SR_S) == 0) { in DISAS_INSN()6127 (sr & SR_S) ? 'S' : 'U', (sr & SR_M) ? '%' : 'I', in m68k_cpu_dump_state()
171 if (env->sr & (1u << SR_S)) { in helper_macl()187 if (env->sr & (1u << SR_S)) { in helper_macw()
47 #define SR_S 1 macro
445 tcg_gen_andi_i32(cpu_sr, cpu_sr, ~(1u << SR_S)); in _decode_opc()464 tcg_gen_ori_i32(cpu_sr, cpu_sr, (1u << SR_S)); in _decode_opc()