Home
last modified time | relevance | path

Searched refs:SR_I3 (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/target/sh4/
H A Dcpu.c111 (1u << SR_I3) | (1u << SR_I2) | (1u << SR_I1) | (1u << SR_I0); in superh_cpu_reset_hold()
H A Dcpu.h43 #define SR_I3 7 macro