| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn301/ |
| H A D | dcn301_panel_cntl.h | 34 SRIR(PWRSEQ_CNTL, CNTL, PANEL_PWRSEQ, id), \
35 SRIR(PWRSEQ_STATE, STATE, PANEL_PWRSEQ, id), \
36 SRIR(PWRSEQ_REF_DIV, REF_DIV, PANEL_PWRSEQ, id), \
37 SRIR(BL_PWM_CNTL, CNTL, BL_PWM, id), \
38 SRIR(BL_PWM_CNTL2, CNTL2, BL_PWM, id), \
39 SRIR(BL_PWM_PERIOD_CNTL, PERIOD_CNTL, BL_PWM, id), \
40 SRIR(BL_PWM_GRP1_REG_LOCK, GRP1_REG_LOCK, BL_PWM, id)
|
| H A D | dcn301_resource.c | 126 #define SRIR(var_name, reg_name, block, id)\ macro
|
| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn201/ |
| H A D | dcn201_resource.c | 259 #define SRIR(var_name, reg_name, block, id)\ macro
|
| /openbmc/openbmc/meta-arm/meta-arm-bsp/documentation/corstone1000/ |
| H A D | software-architecture.rst | 20 certified (`PSA L2 Ready`_) as well as System Ready IR certified(`SRIR cert`_).
|
| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn21/ |
| H A D | dcn21_resource.c | 109 #define SRIR(var_name, reg_name, block, id)\ macro
|
| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn316/ |
| H A D | dcn316_resource.c | 161 #define SRIR(var_name, reg_name, block, id)\ macro
|
| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn315/ |
| H A D | dcn315_resource.c | 173 #define SRIR(var_name, reg_name, block, id)\ macro
|
| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn321/ |
| H A D | dcn321_resource.c | 150 #define SRIR(var_name, reg_name, block, id)\ macro
|
| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn314/ |
| H A D | dcn314_resource.c | 155 #define SRIR(var_name, reg_name, block, id)\ macro
|
| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn31/ |
| H A D | dcn31_resource.c | 139 #define SRIR(var_name, reg_name, block, id)\ macro
|
| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn30/ |
| H A D | dcn30_resource.c | 127 #define SRIR(var_name, reg_name, block, id)\ macro
|
| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn32/ |
| H A D | dcn32_resource.c | 147 #define SRIR(var_name, reg_name, block, id)\ macro
|
| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn20/ |
| H A D | dcn20_resource.c | 148 #define SRIR(var_name, reg_name, block, id)\ macro
|