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Searched refs:SRDS_MAX_LANES (Results 1 – 25 of 29) sorted by relevance

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/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
H A Dls1088a_serdes.c11 u8 lanes[SRDS_MAX_LANES];
12 u8 rcw_lanes[SRDS_MAX_LANES];
55 int is_found, max_lane = SRDS_MAX_LANES; in serdes_get_number()
119 for (i = 0; i < SRDS_MAX_LANES; i++) { in is_serdes_prtcl_valid()
H A Dls1012a_serdes.c12 u8 lanes[SRDS_MAX_LANES];
67 for (i = 0; i < SRDS_MAX_LANES; i++) { in is_serdes_prtcl_valid()
H A Dls1043a_serdes.c12 u8 lanes[SRDS_MAX_LANES];
79 for (i = 0; i < SRDS_MAX_LANES; i++) { in is_serdes_prtcl_valid()
H A Dls1046a_serdes.c12 u8 lanes[SRDS_MAX_LANES];
92 for (i = 0; i < SRDS_MAX_LANES; i++) { in is_serdes_prtcl_valid()
H A Dls2080a_serdes.c11 u8 lanes[SRDS_MAX_LANES];
117 for (i = 0; i < SRDS_MAX_LANES; i++) { in is_serdes_prtcl_valid()
H A Dlx2160a_serdes.c11 u8 lanes[SRDS_MAX_LANES];
126 for (i = 0; i < SRDS_MAX_LANES; i++) { in is_serdes_prtcl_valid()
H A Dfsl_lsch2_serdes.c67 for (i = 0; i < SRDS_MAX_LANES; i++) { in serdes_get_first_lane()
118 for (lane = 0; lane < SRDS_MAX_LANES; lane++) { in serdes_init()
H A Dfsl_lsch3_serdes.c122 for (i = 0; i < SRDS_MAX_LANES; i++) { in serdes_get_first_lane()
151 for (lane = 0; lane < SRDS_MAX_LANES; lane++) { in serdes_init()
/openbmc/u-boot/arch/arm/cpu/armv7/ls102xa/
H A Dls102xa_serdes.c10 static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
34 for (i = 0; i < SRDS_MAX_LANES; i++) { in is_serdes_prtcl_valid()
H A Dfsl_ls1_serdes.c67 for (i = 0; i < SRDS_MAX_LANES; i++) { in serdes_get_first_lane()
89 for (lane = 0; lane < SRDS_MAX_LANES; lane++) { in serdes_init()
/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dt1024_serdes.c12 static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
47 for (i = 0; i < SRDS_MAX_LANES; i++) { in is_serdes_prtcl_valid()
H A Dfsl_corenet_serdes.c63 } lanes[SRDS_MAX_LANES] = {
148 for (i = 0; i < SRDS_MAX_LANES; i++) { in __serdes_get_first_lane()
203 for (lane = first; lane < SRDS_MAX_LANES; lane++) { in __serdes_get_lane_count()
571 for (lane = 0; lane < SRDS_MAX_LANES; lane++) { in fsl_serdes_init()
668 for (lane = 0; lane < SRDS_MAX_LANES; lane++) in fsl_serdes_init()
686 for (lane = 0; lane < SRDS_MAX_LANES; lane++) { in fsl_serdes_init()
H A Dt1040_serdes.c12 static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
61 for (i = 0; i < SRDS_MAX_LANES; i++) { in is_serdes_prtcl_valid()
H A Dp2041_serdes.c12 static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
83 for (i = 0; i < SRDS_MAX_LANES; i++) { in is_serdes_prtcl_valid()
H A Dp4080_serdes.c13 static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
75 for (i = 0; i < SRDS_MAX_LANES; i++) { in is_serdes_prtcl_valid()
H A Dp5040_serdes.c19 static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
94 for (i = 0; i < SRDS_MAX_LANES; i++) { in is_serdes_prtcl_valid()
H A Dfsl_corenet2_serdes.c160 for (i = 0; i < SRDS_MAX_LANES; i++) { in serdes_get_first_lane()
335 for (lane = 0; lane < SRDS_MAX_LANES; lane++) { in serdes_init()
H A Dt2080_serdes.c15 u8 lanes[SRDS_MAX_LANES];
222 for (i = 0; i < SRDS_MAX_LANES; i++) { in is_serdes_prtcl_valid()
H A Dp5020_serdes.c12 static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
128 for (i = 0; i < SRDS_MAX_LANES; i++) { in is_serdes_prtcl_valid()
H A Dp3041_serdes.c12 static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
128 for (i = 0; i < SRDS_MAX_LANES; i++) { in is_serdes_prtcl_valid()
H A Db4860_serdes.c14 u8 lanes[SRDS_MAX_LANES];
279 for (i = 0; i < SRDS_MAX_LANES; i++) { in is_serdes_prtcl_valid()
H A Dcmd_errata.c89 for (lane = 0; lane < SRDS_MAX_LANES; lane++) { in check_erratum_a4580()
H A Dt4240_serdes.c14 u8 lanes[SRDS_MAX_LANES];
511 for (i = 0; i < SRDS_MAX_LANES; i++) { in is_serdes_prtcl_valid()
/openbmc/u-boot/arch/arm/include/asm/arch-fsl-layerscape/
H A Dconfig.h24 #define SRDS_MAX_LANES 8 macro
125 #define SRDS_MAX_LANES 4 macro
183 #define SRDS_MAX_LANES 8 macro
/openbmc/u-boot/board/freescale/lx2160a/
H A Deth_lx2160aqds.c61 } phy_config[SRDS_MAX_LANES];
356 for (i = 0; i < SRDS_MAX_LANES; i++) { in do_phy_config()

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