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Searched refs:SRC_SCR (Results 1 – 5 of 5) sorted by relevance

/openbmc/linux/arch/arm/mach-imx/
H A Dsrc.c19 #define SRC_SCR 0x000 macro
66 val = readl_relaxed(src_base + SRC_SCR); in imx_src_reset_module()
68 writel_relaxed(val, src_base + SRC_SCR); in imx_src_reset_module()
72 while (readl(src_base + SRC_SCR) & bit) { in imx_src_reset_module()
138 val = readl_relaxed(src_base + SRC_SCR); in imx_enable_cpu()
141 writel_relaxed(val, src_base + SRC_SCR); in imx_enable_cpu()
181 val = readl_relaxed(src_base + SRC_SCR); in imx_src_init()
183 writel_relaxed(val, src_base + SRC_SCR); in imx_src_init()
/openbmc/qemu/hw/misc/
H A Dimx6_src.c38 case SRC_SCR: in imx6_src_reg_name()
95 s->regs[SRC_SCR] = 0x521; in imx6_src_reset()
136 s->regs[SRC_SCR] = deposit32(s->regs[SRC_SCR], ri->reset_bit, 1, 0); in imx6_clear_reset_bit()
138 imx6_src_reg_name(SRC_SCR), s->regs[SRC_SCR]); in imx6_clear_reset_bit()
182 case SRC_SCR: in imx6_src_write()
H A Dimx7_src.c29 case SRC_SCR: in imx7_src_reg_name()
100 s->regs[SRC_SCR] = 0xA0; in imx7_src_reset()
/openbmc/qemu/include/hw/misc/
H A Dimx7_src.h17 #define SRC_SCR 0 macro
H A Dimx6_src.h18 #define SRC_SCR 0 macro