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Searched refs:SRC_M4RCR (Results 1 – 3 of 3) sorted by relevance

/openbmc/linux/drivers/reset/
H A Dreset-imx7.c38 SRC_M4RCR = 0x000c, enumerator
68 [IMX7_RESET_SW_M4C_RST] = { SRC_M4RCR, BIT(1) },
69 [IMX7_RESET_SW_M4P_RST] = { SRC_M4RCR, BIT(2) },
180 [IMX8MQ_RESET_SW_NON_SCLR_M4C_RST] = { SRC_M4RCR, BIT(0) },
181 [IMX8MQ_RESET_SW_M4C_RST] = { SRC_M4RCR, BIT(1) },
182 [IMX8MQ_RESET_SW_M4P_RST] = { SRC_M4RCR, BIT(2) },
183 [IMX8MQ_RESET_M4_ENABLE] = { SRC_M4RCR, BIT(3) },
292 [IMX8MP_RESET_SW_NON_SCLR_M7C_RST] = { SRC_M4RCR, BIT(0) },
/openbmc/qemu/include/hw/misc/
H A Dimx7_src.h20 #define SRC_M4RCR 3 macro
/openbmc/qemu/hw/misc/
H A Dimx7_src.c35 case SRC_M4RCR: in imx7_src_reg_name()