1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
4  * Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com>
5  * Copyright(c) 2006 - 2008 Jay Cliburn <jcliburn@gmail.com>
6  *
7  * Derived from Intel e1000 driver
8  * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
9  */
10 
11 #ifndef ATL1_H
12 #define ATL1_H
13 
14 #include <linux/compiler.h>
15 #include <linux/ethtool.h>
16 #include <linux/if_vlan.h>
17 #include <linux/mii.h>
18 #include <linux/module.h>
19 #include <linux/skbuff.h>
20 #include <linux/spinlock.h>
21 #include <linux/timer.h>
22 #include <linux/types.h>
23 #include <linux/workqueue.h>
24 
25 #include "atlx.h"
26 
27 #define ATLX_DRIVER_NAME "atl1"
28 
29 MODULE_DESCRIPTION("Atheros L1 Gigabit Ethernet Driver");
30 
31 #define atlx_adapter		atl1_adapter
32 #define atlx_check_for_link	atl1_check_for_link
33 #define atlx_check_link		atl1_check_link
34 #define atlx_hash_mc_addr	atl1_hash_mc_addr
35 #define atlx_hash_set		atl1_hash_set
36 #define atlx_hw			atl1_hw
37 #define atlx_mii_ioctl		atl1_mii_ioctl
38 #define atlx_read_phy_reg	atl1_read_phy_reg
39 #define atlx_set_mac		atl1_set_mac
40 #define atlx_set_mac_addr	atl1_set_mac_addr
41 
42 struct atl1_adapter;
43 struct atl1_hw;
44 
45 /* function prototypes needed by multiple files */
46 static u32 atl1_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr);
47 static void atl1_hash_set(struct atl1_hw *hw, u32 hash_value);
48 static void atl1_set_mac_addr(struct atl1_hw *hw);
49 static int atl1_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
50 	int cmd);
51 static u32 atl1_check_link(struct atl1_adapter *adapter);
52 
53 /* hardware definitions specific to L1 */
54 
55 /* Block IDLE Status Register */
56 #define IDLE_STATUS_RXMAC			0x1
57 #define IDLE_STATUS_TXMAC			0x2
58 #define IDLE_STATUS_RXQ				0x4
59 #define IDLE_STATUS_TXQ				0x8
60 #define IDLE_STATUS_DMAR			0x10
61 #define IDLE_STATUS_DMAW			0x20
62 #define IDLE_STATUS_SMB				0x40
63 #define IDLE_STATUS_CMB				0x80
64 
65 /* MDIO Control Register */
66 #define MDIO_WAIT_TIMES				30
67 
68 /* MAC Control Register */
69 #define MAC_CTRL_TX_PAUSE			0x10000
70 #define MAC_CTRL_SCNT				0x20000
71 #define MAC_CTRL_SRST_TX			0x40000
72 #define MAC_CTRL_TX_SIMURST			0x80000
73 #define MAC_CTRL_SPEED_SHIFT			20
74 #define MAC_CTRL_SPEED_MASK			0x300000
75 #define MAC_CTRL_SPEED_1000			0x2
76 #define MAC_CTRL_SPEED_10_100			0x1
77 #define MAC_CTRL_DBG_TX_BKPRESURE		0x400000
78 #define MAC_CTRL_TX_HUGE			0x800000
79 #define MAC_CTRL_RX_CHKSUM_EN			0x1000000
80 #define MAC_CTRL_DBG				0x8000000
81 
82 /* Wake-On-Lan control register */
83 #define WOL_CLK_SWITCH_EN			0x8000
84 #define WOL_PT5_EN				0x200000
85 #define WOL_PT6_EN				0x400000
86 #define WOL_PT5_MATCH				0x8000000
87 #define WOL_PT6_MATCH				0x10000000
88 
89 /* WOL Length ( 2 DWORD ) */
90 #define REG_WOL_PATTERN_LEN			0x14A4
91 #define WOL_PT_LEN_MASK				0x7F
92 #define WOL_PT0_LEN_SHIFT			0
93 #define WOL_PT1_LEN_SHIFT			8
94 #define WOL_PT2_LEN_SHIFT			16
95 #define WOL_PT3_LEN_SHIFT			24
96 #define WOL_PT4_LEN_SHIFT			0
97 #define WOL_PT5_LEN_SHIFT			8
98 #define WOL_PT6_LEN_SHIFT			16
99 
100 /* Internal SRAM Partition Registers, low 32 bits */
101 #define REG_SRAM_RFD_LEN			0x1504
102 #define REG_SRAM_RRD_ADDR			0x1508
103 #define REG_SRAM_RRD_LEN			0x150C
104 #define REG_SRAM_TPD_ADDR			0x1510
105 #define REG_SRAM_TPD_LEN			0x1514
106 #define REG_SRAM_TRD_ADDR			0x1518
107 #define REG_SRAM_TRD_LEN			0x151C
108 #define REG_SRAM_RXF_ADDR			0x1520
109 #define REG_SRAM_RXF_LEN			0x1524
110 #define REG_SRAM_TXF_ADDR			0x1528
111 #define REG_SRAM_TXF_LEN			0x152C
112 #define REG_SRAM_TCPH_PATH_ADDR			0x1530
113 #define SRAM_TCPH_ADDR_MASK			0xFFF
114 #define SRAM_TCPH_ADDR_SHIFT			0
115 #define SRAM_PATH_ADDR_MASK			0xFFF
116 #define SRAM_PATH_ADDR_SHIFT			16
117 
118 /* Load Ptr Register */
119 #define REG_LOAD_PTR				0x1534
120 
121 /* Descriptor Control registers, low 32 bits */
122 #define REG_DESC_RFD_ADDR_LO			0x1544
123 #define REG_DESC_RRD_ADDR_LO			0x1548
124 #define REG_DESC_TPD_ADDR_LO			0x154C
125 #define REG_DESC_CMB_ADDR_LO			0x1550
126 #define REG_DESC_SMB_ADDR_LO			0x1554
127 #define REG_DESC_RFD_RRD_RING_SIZE		0x1558
128 #define DESC_RFD_RING_SIZE_MASK			0x7FF
129 #define DESC_RFD_RING_SIZE_SHIFT		0
130 #define DESC_RRD_RING_SIZE_MASK			0x7FF
131 #define DESC_RRD_RING_SIZE_SHIFT		16
132 #define REG_DESC_TPD_RING_SIZE			0x155C
133 #define DESC_TPD_RING_SIZE_MASK			0x3FF
134 #define DESC_TPD_RING_SIZE_SHIFT		0
135 
136 /* TXQ Control Register */
137 #define REG_TXQ_CTRL				0x1580
138 #define TXQ_CTRL_TPD_BURST_NUM_SHIFT		0
139 #define TXQ_CTRL_TPD_BURST_NUM_MASK		0x1F
140 #define TXQ_CTRL_EN				0x20
141 #define TXQ_CTRL_ENH_MODE			0x40
142 #define TXQ_CTRL_TPD_FETCH_TH_SHIFT		8
143 #define TXQ_CTRL_TPD_FETCH_TH_MASK		0x3F
144 #define TXQ_CTRL_TXF_BURST_NUM_SHIFT		16
145 #define TXQ_CTRL_TXF_BURST_NUM_MASK		0xFFFF
146 
147 /* Jumbo packet Threshold for task offload */
148 #define REG_TX_JUMBO_TASK_TH_TPD_IPG		0x1584
149 #define TX_JUMBO_TASK_TH_MASK			0x7FF
150 #define TX_JUMBO_TASK_TH_SHIFT			0
151 #define TX_TPD_MIN_IPG_MASK			0x1F
152 #define TX_TPD_MIN_IPG_SHIFT			16
153 
154 /* RXQ Control Register */
155 #define REG_RXQ_CTRL				0x15A0
156 #define RXQ_CTRL_RFD_BURST_NUM_SHIFT		0
157 #define RXQ_CTRL_RFD_BURST_NUM_MASK		0xFF
158 #define RXQ_CTRL_RRD_BURST_THRESH_SHIFT		8
159 #define RXQ_CTRL_RRD_BURST_THRESH_MASK		0xFF
160 #define RXQ_CTRL_RFD_PREF_MIN_IPG_SHIFT		16
161 #define RXQ_CTRL_RFD_PREF_MIN_IPG_MASK		0x1F
162 #define RXQ_CTRL_CUT_THRU_EN			0x40000000
163 #define RXQ_CTRL_EN				0x80000000
164 
165 /* Rx jumbo packet threshold and rrd  retirement timer */
166 #define REG_RXQ_JMBOSZ_RRDTIM			0x15A4
167 #define RXQ_JMBOSZ_TH_MASK			0x7FF
168 #define RXQ_JMBOSZ_TH_SHIFT			0
169 #define RXQ_JMBO_LKAH_MASK			0xF
170 #define RXQ_JMBO_LKAH_SHIFT			11
171 #define RXQ_RRD_TIMER_MASK			0xFFFF
172 #define RXQ_RRD_TIMER_SHIFT			16
173 
174 /* RFD flow control register */
175 #define REG_RXQ_RXF_PAUSE_THRESH		0x15A8
176 #define RXQ_RXF_PAUSE_TH_HI_SHIFT		16
177 #define RXQ_RXF_PAUSE_TH_HI_MASK		0xFFF
178 #define RXQ_RXF_PAUSE_TH_LO_SHIFT		0
179 #define RXQ_RXF_PAUSE_TH_LO_MASK		0xFFF
180 
181 /* RRD flow control register */
182 #define REG_RXQ_RRD_PAUSE_THRESH		0x15AC
183 #define RXQ_RRD_PAUSE_TH_HI_SHIFT		0
184 #define RXQ_RRD_PAUSE_TH_HI_MASK		0xFFF
185 #define RXQ_RRD_PAUSE_TH_LO_SHIFT		16
186 #define RXQ_RRD_PAUSE_TH_LO_MASK		0xFFF
187 
188 /* DMA Engine Control Register */
189 #define REG_DMA_CTRL				0x15C0
190 #define DMA_CTRL_DMAR_IN_ORDER			0x1
191 #define DMA_CTRL_DMAR_ENH_ORDER			0x2
192 #define DMA_CTRL_DMAR_OUT_ORDER			0x4
193 #define DMA_CTRL_RCB_VALUE			0x8
194 #define DMA_CTRL_DMAR_BURST_LEN_SHIFT		4
195 #define DMA_CTRL_DMAR_BURST_LEN_MASK		7
196 #define DMA_CTRL_DMAW_BURST_LEN_SHIFT		7
197 #define DMA_CTRL_DMAW_BURST_LEN_MASK		7
198 #define DMA_CTRL_DMAR_EN			0x400
199 #define DMA_CTRL_DMAW_EN			0x800
200 
201 /* CMB/SMB Control Register */
202 #define REG_CSMB_CTRL				0x15D0
203 #define CSMB_CTRL_CMB_NOW			1
204 #define CSMB_CTRL_SMB_NOW			2
205 #define CSMB_CTRL_CMB_EN			4
206 #define CSMB_CTRL_SMB_EN			8
207 
208 /* CMB DMA Write Threshold Register */
209 #define REG_CMB_WRITE_TH			0x15D4
210 #define CMB_RRD_TH_SHIFT			0
211 #define CMB_RRD_TH_MASK				0x7FF
212 #define CMB_TPD_TH_SHIFT			16
213 #define CMB_TPD_TH_MASK				0x7FF
214 
215 /* RX/TX count-down timer to trigger CMB-write. 2us resolution. */
216 #define REG_CMB_WRITE_TIMER			0x15D8
217 #define CMB_RX_TM_SHIFT				0
218 #define CMB_RX_TM_MASK				0xFFFF
219 #define CMB_TX_TM_SHIFT				16
220 #define CMB_TX_TM_MASK				0xFFFF
221 
222 /* Number of packet received since last CMB write */
223 #define REG_CMB_RX_PKT_CNT			0x15DC
224 
225 /* Number of packet transmitted since last CMB write */
226 #define REG_CMB_TX_PKT_CNT			0x15E0
227 
228 /* SMB auto DMA timer register */
229 #define REG_SMB_TIMER				0x15E4
230 
231 /* Mailbox Register */
232 #define REG_MAILBOX				0x15F0
233 #define MB_RFD_PROD_INDX_SHIFT			0
234 #define MB_RFD_PROD_INDX_MASK			0x7FF
235 #define MB_RRD_CONS_INDX_SHIFT			11
236 #define MB_RRD_CONS_INDX_MASK			0x7FF
237 #define MB_TPD_PROD_INDX_SHIFT			22
238 #define MB_TPD_PROD_INDX_MASK			0x3FF
239 
240 /* Interrupt Status Register */
241 #define ISR_SMB					0x1
242 #define ISR_TIMER				0x2
243 #define ISR_MANUAL				0x4
244 #define ISR_RXF_OV				0x8
245 #define ISR_RFD_UNRUN				0x10
246 #define ISR_RRD_OV				0x20
247 #define ISR_TXF_UNRUN				0x40
248 #define ISR_LINK				0x80
249 #define ISR_HOST_RFD_UNRUN			0x100
250 #define ISR_HOST_RRD_OV				0x200
251 #define ISR_DMAR_TO_RST				0x400
252 #define ISR_DMAW_TO_RST				0x800
253 #define ISR_GPHY				0x1000
254 #define ISR_RX_PKT				0x10000
255 #define ISR_TX_PKT				0x20000
256 #define ISR_TX_DMA				0x40000
257 #define ISR_RX_DMA				0x80000
258 #define ISR_CMB_RX				0x100000
259 #define ISR_CMB_TX				0x200000
260 #define ISR_MAC_RX				0x400000
261 #define ISR_MAC_TX				0x800000
262 #define ISR_DIS_SMB				0x20000000
263 #define ISR_DIS_DMA				0x40000000
264 
265 /* Normal Interrupt mask without RX/TX enabled */
266 #define IMR_NORXTX_MASK	(\
267 	ISR_SMB		|\
268 	ISR_GPHY	|\
269 	ISR_PHY_LINKDOWN|\
270 	ISR_DMAR_TO_RST	|\
271 	ISR_DMAW_TO_RST)
272 
273 /* Normal Interrupt mask  */
274 #define IMR_NORMAL_MASK	(\
275 	IMR_NORXTX_MASK	|\
276 	ISR_CMB_TX	|\
277 	ISR_CMB_RX)
278 
279 /* Debug Interrupt Mask  (enable all interrupt) */
280 #define IMR_DEBUG_MASK	(\
281 	ISR_SMB		|\
282 	ISR_TIMER	|\
283 	ISR_MANUAL	|\
284 	ISR_RXF_OV	|\
285 	ISR_RFD_UNRUN	|\
286 	ISR_RRD_OV	|\
287 	ISR_TXF_UNRUN	|\
288 	ISR_LINK	|\
289 	ISR_CMB_TX	|\
290 	ISR_CMB_RX	|\
291 	ISR_RX_PKT	|\
292 	ISR_TX_PKT	|\
293 	ISR_MAC_RX	|\
294 	ISR_MAC_TX)
295 
296 #define MEDIA_TYPE_1000M_FULL			1
297 #define MEDIA_TYPE_100M_FULL			2
298 #define MEDIA_TYPE_100M_HALF			3
299 #define MEDIA_TYPE_10M_FULL			4
300 #define MEDIA_TYPE_10M_HALF			5
301 
302 #define AUTONEG_ADVERTISE_SPEED_DEFAULT		0x002F	/* All but 1000-Half */
303 
304 #define MAX_JUMBO_FRAME_SIZE			10240
305 
306 #define ATL1_EEDUMP_LEN				48
307 
308 /* Statistics counters collected by the MAC */
309 struct stats_msg_block {
310 	/* rx */
311 	u32 rx_ok;		/* good RX packets */
312 	u32 rx_bcast;		/* good RX broadcast packets */
313 	u32 rx_mcast;		/* good RX multicast packets */
314 	u32 rx_pause;		/* RX pause frames */
315 	u32 rx_ctrl;		/* RX control packets other than pause frames */
316 	u32 rx_fcs_err;		/* RX packets with bad FCS */
317 	u32 rx_len_err;		/* RX packets with length != actual size */
318 	u32 rx_byte_cnt;	/* good bytes received. FCS is NOT included */
319 	u32 rx_runt;		/* RX packets < 64 bytes with good FCS */
320 	u32 rx_frag;		/* RX packets < 64 bytes with bad FCS */
321 	u32 rx_sz_64;		/* 64 byte RX packets */
322 	u32 rx_sz_65_127;
323 	u32 rx_sz_128_255;
324 	u32 rx_sz_256_511;
325 	u32 rx_sz_512_1023;
326 	u32 rx_sz_1024_1518;
327 	u32 rx_sz_1519_max;	/* 1519 byte to MTU RX packets */
328 	u32 rx_sz_ov;		/* truncated RX packets > MTU */
329 	u32 rx_rxf_ov;		/* frames dropped due to RX FIFO overflow */
330 	u32 rx_rrd_ov;		/* frames dropped due to RRD overflow */
331 	u32 rx_align_err;	/* alignment errors */
332 	u32 rx_bcast_byte_cnt;	/* RX broadcast bytes, excluding FCS */
333 	u32 rx_mcast_byte_cnt;	/* RX multicast bytes, excluding FCS */
334 	u32 rx_err_addr;	/* packets dropped due to address filtering */
335 
336 	/* tx */
337 	u32 tx_ok;		/* good TX packets */
338 	u32 tx_bcast;		/* good TX broadcast packets */
339 	u32 tx_mcast;		/* good TX multicast packets */
340 	u32 tx_pause;		/* TX pause frames */
341 	u32 tx_exc_defer;	/* TX packets deferred excessively */
342 	u32 tx_ctrl;		/* TX control frames, excluding pause frames */
343 	u32 tx_defer;		/* TX packets deferred */
344 	u32 tx_byte_cnt;	/* bytes transmitted, FCS is NOT included */
345 	u32 tx_sz_64;		/* 64 byte TX packets */
346 	u32 tx_sz_65_127;
347 	u32 tx_sz_128_255;
348 	u32 tx_sz_256_511;
349 	u32 tx_sz_512_1023;
350 	u32 tx_sz_1024_1518;
351 	u32 tx_sz_1519_max;	/* 1519 byte to MTU TX packets */
352 	u32 tx_1_col;		/* packets TX after a single collision */
353 	u32 tx_2_col;		/* packets TX after multiple collisions */
354 	u32 tx_late_col;	/* TX packets with late collisions */
355 	u32 tx_abort_col;	/* TX packets aborted w/excessive collisions */
356 	u32 tx_underrun;	/* TX packets aborted due to TX FIFO underrun
357 				 * or TRD FIFO underrun */
358 	u32 tx_rd_eop;		/* reads beyond the EOP into the next frame
359 				 * when TRD was not written timely */
360 	u32 tx_len_err;		/* TX packets where length != actual size */
361 	u32 tx_trunc;		/* TX packets truncated due to size > MTU */
362 	u32 tx_bcast_byte;	/* broadcast bytes transmitted, excluding FCS */
363 	u32 tx_mcast_byte;	/* multicast bytes transmitted, excluding FCS */
364 	u32 smb_updated;	/* 1: SMB Updated. This is used by software to
365 				 * indicate the statistics update. Software
366 				 * should clear this bit after retrieving the
367 				 * statistics information. */
368 };
369 
370 /* Coalescing Message Block */
371 struct coals_msg_block {
372 	u32 int_stats;		/* interrupt status */
373 	u16 rrd_prod_idx;	/* TRD Producer Index. */
374 	u16 rfd_cons_idx;	/* RFD Consumer Index. */
375 	u16 update;		/* Selene sets this bit every time it DMAs the
376 				 * CMB to host memory. Software should clear
377 				 * this bit when CMB info is processed. */
378 	u16 tpd_cons_idx;	/* TPD Consumer Index. */
379 };
380 
381 /* RRD descriptor */
382 struct rx_return_desc {
383 	u8 num_buf;	/* Number of RFD buffers used by the received packet */
384 	u8 resved;
385 	u16 buf_indx;	/* RFD Index of the first buffer */
386 	union {
387 		u32 valid;
388 		struct {
389 			u16 rx_chksum;
390 			u16 pkt_size;
391 		} xsum_sz;
392 	} xsz;
393 
394 	u16 pkt_flg;	/* Packet flags */
395 	u16 err_flg;	/* Error flags */
396 	u16 resved2;
397 	u16 vlan_tag;	/* VLAN TAG */
398 };
399 
400 #define PACKET_FLAG_ETH_TYPE	0x0080
401 #define PACKET_FLAG_VLAN_INS	0x0100
402 #define PACKET_FLAG_ERR		0x0200
403 #define PACKET_FLAG_IPV4	0x0400
404 #define PACKET_FLAG_UDP		0x0800
405 #define PACKET_FLAG_TCP		0x1000
406 #define PACKET_FLAG_BCAST	0x2000
407 #define PACKET_FLAG_MCAST	0x4000
408 #define PACKET_FLAG_PAUSE	0x8000
409 
410 #define ERR_FLAG_CRC		0x0001
411 #define ERR_FLAG_CODE		0x0002
412 #define ERR_FLAG_DRIBBLE	0x0004
413 #define ERR_FLAG_RUNT		0x0008
414 #define ERR_FLAG_OV		0x0010
415 #define ERR_FLAG_TRUNC		0x0020
416 #define ERR_FLAG_IP_CHKSUM	0x0040
417 #define ERR_FLAG_L4_CHKSUM	0x0080
418 #define ERR_FLAG_LEN		0x0100
419 #define ERR_FLAG_DES_ADDR	0x0200
420 
421 /* RFD descriptor */
422 struct rx_free_desc {
423 	__le64 buffer_addr;	/* Address of the descriptor's data buffer */
424 	__le16 buf_len;		/* Size of the receive buffer in host memory */
425 	u16 coalese;		/* Update consumer index to host after the
426 				 * reception of this frame */
427 	/* __packed is required */
428 } __packed;
429 
430 /*
431  * The L1 transmit packet descriptor is comprised of four 32-bit words.
432  *
433  *	31					0
434  *	+---------------------------------------+
435  *      |	Word 0: Buffer addr lo 		|
436  *      +---------------------------------------+
437  *      |	Word 1: Buffer addr hi		|
438  *      +---------------------------------------+
439  *      |		Word 2			|
440  *      +---------------------------------------+
441  *      |		Word 3			|
442  *      +---------------------------------------+
443  *
444  * Words 0 and 1 combine to form a 64-bit buffer address.
445  *
446  * Word 2 is self explanatory in the #define block below.
447  *
448  * Word 3 has two forms, depending upon the state of bits 3 and 4.
449  * If bits 3 and 4 are both zero, then bits 14:31 are unused by the
450  * hardware.  Otherwise, if either bit 3 or 4 is set, the definition
451  * of bits 14:31 vary according to the following depiction.
452  *
453  *	0	End of packet			0	End of packet
454  *	1	Coalesce			1	Coalesce
455  *	2	Insert VLAN tag			2	Insert VLAN tag
456  *	3	Custom csum enable = 0		3	Custom csum enable = 1
457  *	4	Segment enable = 1		4	Segment enable = 0
458  *	5	Generate IP checksum		5	Generate IP checksum
459  *	6	Generate TCP checksum		6	Generate TCP checksum
460  *	7	Generate UDP checksum		7	Generate UDP checksum
461  *	8	VLAN tagged			8	VLAN tagged
462  *	9	Ethernet frame type		9	Ethernet frame type
463  *	10-+ 					10-+
464  *	11 |	IP hdr length (10:13)		11 |	IP hdr length (10:13)
465  *	12 |	(num 32-bit words)		12 |	(num 32-bit words)
466  *	13-+					13-+
467  *	14-+					14	Unused
468  *	15 |	TCP hdr length (14:17)		15	Unused
469  *	16 |	(num 32-bit words)		16-+
470  *	17-+					17 |
471  *	18	Header TPD flag			18 |
472  *	19-+					19 |	Payload offset
473  *	20 |					20 |	    (16:23)
474  *	21 |					21 |
475  *	22 |					22 |
476  *	23 |					23-+
477  *	24 |					24-+
478  *	25 |	MSS (19:31)			25 |
479  *	26 |					26 |
480  *	27 |					27 |	Custom csum offset
481  *	28 |					28 |	     (24:31)
482  *	29 |					29 |
483  *	30 |					30 |
484  *	31-+					31-+
485  */
486 
487 /* tpd word 2 */
488 #define TPD_BUFLEN_MASK		0x3FFF
489 #define TPD_BUFLEN_SHIFT	0
490 #define TPD_DMAINT_MASK		0x0001
491 #define TPD_DMAINT_SHIFT	14
492 #define TPD_PKTNT_MASK		0x0001
493 #define TPD_PKTINT_SHIFT	15
494 #define TPD_VLANTAG_MASK	0xFFFF
495 #define TPD_VLANTAG_SHIFT	16
496 
497 /* tpd word 3 bits 0:13 */
498 #define TPD_EOP_MASK		0x0001
499 #define TPD_EOP_SHIFT		0
500 #define TPD_COALESCE_MASK	0x0001
501 #define TPD_COALESCE_SHIFT	1
502 #define TPD_INS_VL_TAG_MASK	0x0001
503 #define TPD_INS_VL_TAG_SHIFT	2
504 #define TPD_CUST_CSUM_EN_MASK	0x0001
505 #define TPD_CUST_CSUM_EN_SHIFT	3
506 #define TPD_SEGMENT_EN_MASK	0x0001
507 #define TPD_SEGMENT_EN_SHIFT	4
508 #define TPD_IP_CSUM_MASK	0x0001
509 #define TPD_IP_CSUM_SHIFT	5
510 #define TPD_TCP_CSUM_MASK	0x0001
511 #define TPD_TCP_CSUM_SHIFT	6
512 #define TPD_UDP_CSUM_MASK	0x0001
513 #define TPD_UDP_CSUM_SHIFT	7
514 #define TPD_VL_TAGGED_MASK	0x0001
515 #define TPD_VL_TAGGED_SHIFT	8
516 #define TPD_ETHTYPE_MASK	0x0001
517 #define TPD_ETHTYPE_SHIFT	9
518 #define TPD_IPHL_MASK		0x000F
519 #define TPD_IPHL_SHIFT		10
520 
521 /* tpd word 3 bits 14:31 if segment enabled */
522 #define TPD_TCPHDRLEN_MASK	0x000F
523 #define TPD_TCPHDRLEN_SHIFT	14
524 #define TPD_HDRFLAG_MASK	0x0001
525 #define TPD_HDRFLAG_SHIFT	18
526 #define TPD_MSS_MASK		0x1FFF
527 #define TPD_MSS_SHIFT		19
528 
529 /* tpd word 3 bits 16:31 if custom csum enabled */
530 #define TPD_PLOADOFFSET_MASK	0x00FF
531 #define TPD_PLOADOFFSET_SHIFT	16
532 #define TPD_CCSUMOFFSET_MASK	0x00FF
533 #define TPD_CCSUMOFFSET_SHIFT	24
534 
535 struct tx_packet_desc {
536 	__le64 buffer_addr;
537 	__le32 word2;
538 	__le32 word3;
539 };
540 
541 /* DMA Order Settings */
542 enum atl1_dma_order {
543 	atl1_dma_ord_in = 1,
544 	atl1_dma_ord_enh = 2,
545 	atl1_dma_ord_out = 4
546 };
547 
548 enum atl1_dma_rcb {
549 	atl1_rcb_64 = 0,
550 	atl1_rcb_128 = 1
551 };
552 
553 enum atl1_dma_req_block {
554 	atl1_dma_req_128 = 0,
555 	atl1_dma_req_256 = 1,
556 	atl1_dma_req_512 = 2,
557 	atl1_dma_req_1024 = 3,
558 	atl1_dma_req_2048 = 4,
559 	atl1_dma_req_4096 = 5
560 };
561 
562 #define ATL1_MAX_INTR		3
563 #define ATL1_MAX_TX_BUF_LEN	0x3000	/* 12288 bytes */
564 
565 #define ATL1_DEFAULT_TPD	256
566 #define ATL1_MAX_TPD		1024
567 #define ATL1_MIN_TPD		64
568 #define ATL1_DEFAULT_RFD	512
569 #define ATL1_MIN_RFD		128
570 #define ATL1_MAX_RFD		2048
571 #define ATL1_REG_COUNT		1538
572 
573 #define ATL1_GET_DESC(R, i, type)	(&(((type *)((R)->desc))[i]))
574 #define ATL1_RFD_DESC(R, i)	ATL1_GET_DESC(R, i, struct rx_free_desc)
575 #define ATL1_TPD_DESC(R, i)	ATL1_GET_DESC(R, i, struct tx_packet_desc)
576 #define ATL1_RRD_DESC(R, i)	ATL1_GET_DESC(R, i, struct rx_return_desc)
577 
578 /*
579  * atl1_ring_header represents a single, contiguous block of DMA space
580  * mapped for the three descriptor rings (tpd, rfd, rrd) and the two
581  * message blocks (cmb, smb) described below
582  */
583 struct atl1_ring_header {
584 	void *desc;		/* virtual address */
585 	dma_addr_t dma;		/* physical address*/
586 	unsigned int size;	/* length in bytes */
587 };
588 
589 /*
590  * atl1_buffer is wrapper around a pointer to a socket buffer
591  * so a DMA handle can be stored along with the skb
592  */
593 struct atl1_buffer {
594 	struct sk_buff *skb;	/* socket buffer */
595 	u16 length;		/* rx buffer length */
596 	u16 alloced;		/* 1 if skb allocated */
597 	dma_addr_t dma;
598 };
599 
600 /* transmit packet descriptor (tpd) ring */
601 struct atl1_tpd_ring {
602 	void *desc;		/* descriptor ring virtual address */
603 	dma_addr_t dma;		/* descriptor ring physical address */
604 	u16 size;		/* descriptor ring length in bytes */
605 	u16 count;		/* number of descriptors in the ring */
606 	u16 hw_idx;		/* hardware index */
607 	atomic_t next_to_clean;
608 	atomic_t next_to_use;
609 	struct atl1_buffer *buffer_info;
610 };
611 
612 /* receive free descriptor (rfd) ring */
613 struct atl1_rfd_ring {
614 	void *desc;		/* descriptor ring virtual address */
615 	dma_addr_t dma;		/* descriptor ring physical address */
616 	u16 size;		/* descriptor ring length in bytes */
617 	u16 count;		/* number of descriptors in the ring */
618 	atomic_t next_to_use;
619 	u16 next_to_clean;
620 	struct atl1_buffer *buffer_info;
621 };
622 
623 /* receive return descriptor (rrd) ring */
624 struct atl1_rrd_ring {
625 	void *desc;		/* descriptor ring virtual address */
626 	dma_addr_t dma;		/* descriptor ring physical address */
627 	unsigned int size;	/* descriptor ring length in bytes */
628 	u16 count;		/* number of descriptors in the ring */
629 	u16 next_to_use;
630 	atomic_t next_to_clean;
631 };
632 
633 /* coalescing message block (cmb) */
634 struct atl1_cmb {
635 	struct coals_msg_block *cmb;
636 	dma_addr_t dma;
637 };
638 
639 /* statistics message block (smb) */
640 struct atl1_smb {
641 	struct stats_msg_block *smb;
642 	dma_addr_t dma;
643 };
644 
645 /* Statistics counters */
646 struct atl1_sft_stats {
647 	u64 rx_packets;
648 	u64 tx_packets;
649 	u64 rx_bytes;
650 	u64 tx_bytes;
651 	u64 multicast;
652 	u64 collisions;
653 	u64 rx_errors;
654 	u64 rx_length_errors;
655 	u64 rx_crc_errors;
656 	u64 rx_dropped;
657 	u64 rx_frame_errors;
658 	u64 rx_fifo_errors;
659 	u64 rx_missed_errors;
660 	u64 tx_errors;
661 	u64 tx_fifo_errors;
662 	u64 tx_aborted_errors;
663 	u64 tx_window_errors;
664 	u64 tx_carrier_errors;
665 	u64 tx_pause;		/* TX pause frames */
666 	u64 excecol;		/* TX packets w/ excessive collisions */
667 	u64 deffer;		/* TX packets deferred */
668 	u64 scc;		/* packets TX after a single collision */
669 	u64 mcc;		/* packets TX after multiple collisions */
670 	u64 latecol;		/* TX packets w/ late collisions */
671 	u64 tx_underrun;	/* TX packets aborted due to TX FIFO underrun
672 				 * or TRD FIFO underrun */
673 	u64 tx_trunc;		/* TX packets truncated due to size > MTU */
674 	u64 rx_pause;		/* num Pause packets received. */
675 	u64 rx_rrd_ov;
676 	u64 rx_trunc;
677 };
678 
679 /* hardware structure */
680 struct atl1_hw {
681 	u8 __iomem *hw_addr;
682 	struct atl1_adapter *back;
683 	enum atl1_dma_order dma_ord;
684 	enum atl1_dma_rcb rcb_value;
685 	enum atl1_dma_req_block dmar_block;
686 	enum atl1_dma_req_block dmaw_block;
687 	u8 preamble_len;
688 	u8 max_retry;
689 	u8 jam_ipg;		/* IPG to start JAM for collision based flow
690 				 * control in half-duplex mode. In units of
691 				 * 8-bit time */
692 	u8 ipgt;		/* Desired back to back inter-packet gap.
693 				 * The default is 96-bit time */
694 	u8 min_ifg;		/* Minimum number of IFG to enforce in between
695 				 * receive frames. Frame gap below such IFP
696 				 * is dropped */
697 	u8 ipgr1;		/* 64bit Carrier-Sense window */
698 	u8 ipgr2;		/* 96-bit IPG window */
699 	u8 tpd_burst;		/* Number of TPD to prefetch in cache-aligned
700 				 * burst. Each TPD is 16 bytes long */
701 	u8 rfd_burst;		/* Number of RFD to prefetch in cache-aligned
702 				 * burst. Each RFD is 12 bytes long */
703 	u8 rfd_fetch_gap;
704 	u8 rrd_burst;		/* Threshold number of RRDs that can be retired
705 				 * in a burst. Each RRD is 16 bytes long */
706 	u8 tpd_fetch_th;
707 	u8 tpd_fetch_gap;
708 	u16 tx_jumbo_task_th;
709 	u16 txf_burst;		/* Number of data bytes to read in a cache-
710 				 * aligned burst. Each SRAM entry is 8 bytes */
711 	u16 rx_jumbo_th;	/* Jumbo packet size for non-VLAN packet. VLAN
712 				 * packets should add 4 bytes */
713 	u16 rx_jumbo_lkah;
714 	u16 rrd_ret_timer;	/* RRD retirement timer. Decrement by 1 after
715 				 * every 512ns passes. */
716 	u16 lcol;		/* Collision Window */
717 
718 	u16 cmb_tpd;
719 	u16 cmb_rrd;
720 	u16 cmb_rx_timer;
721 	u16 cmb_tx_timer;
722 	u32 smb_timer;
723 	u16 media_type;
724 	u16 autoneg_advertised;
725 
726 	u16 mii_autoneg_adv_reg;
727 	u16 mii_1000t_ctrl_reg;
728 
729 	u32 max_frame_size;
730 	u32 min_frame_size;
731 
732 	u16 dev_rev;
733 
734 	/* spi flash */
735 	u8 flash_vendor;
736 
737 	u8 mac_addr[ETH_ALEN];
738 	u8 perm_mac_addr[ETH_ALEN];
739 
740 	bool phy_configured;
741 };
742 
743 struct atl1_adapter {
744 	struct net_device *netdev;
745 	struct pci_dev *pdev;
746 
747 	struct atl1_sft_stats soft_stats;
748 	u32 rx_buffer_len;
749 	u32 wol;
750 	u16 link_speed;
751 	u16 link_duplex;
752 	spinlock_t lock;
753 	struct napi_struct napi;
754 	struct work_struct reset_dev_task;
755 	struct work_struct link_chg_task;
756 
757 	struct timer_list phy_config_timer;
758 	bool phy_timer_pending;
759 
760 	/* all descriptor rings' memory */
761 	struct atl1_ring_header ring_header;
762 
763 	/* TX */
764 	struct atl1_tpd_ring tpd_ring;
765 	spinlock_t mb_lock;
766 
767 	/* RX */
768 	struct atl1_rfd_ring rfd_ring;
769 	struct atl1_rrd_ring rrd_ring;
770 	u64 hw_csum_err;
771 	u64 hw_csum_good;
772 	u32 msg_enable;
773 	u16 imt;		/* interrupt moderator timer (2us resolution) */
774 	u16 ict;		/* interrupt clear timer (2us resolution */
775 	struct mii_if_info mii;	/* MII interface info */
776 
777 	/*
778 	 * Use this value to check is napi handler allowed to
779 	 * enable ints or not
780 	 */
781 	bool int_enabled;
782 
783 	u32 bd_number;		/* board number */
784 	bool pci_using_64;
785 	struct atl1_hw hw;
786 	struct atl1_smb smb;
787 	struct atl1_cmb cmb;
788 };
789 
790 #endif /* ATL1_H */
791