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Searched refs:SQ_WAVE_STATUS__VCCZ_MASK (Results 1 – 13 of 13) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h10004 #define SQ_WAVE_STATUS__VCCZ_MASK 0x00000400L macro
H A Dgfx_7_2_sh_mask.h12495 #define SQ_WAVE_STATUS__VCCZ_MASK 0x400 macro
H A Dgfx_8_0_sh_mask.h14375 #define SQ_WAVE_STATUS__VCCZ_MASK 0x400 macro
H A Dgfx_8_1_sh_mask.h14773 #define SQ_WAVE_STATUS__VCCZ_MASK 0x400 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h28441 #define SQ_WAVE_STATUS__VCCZ_MASK … macro
H A Dgc_9_2_1_sh_mask.h29983 #define SQ_WAVE_STATUS__VCCZ_MASK … macro
H A Dgc_9_1_sh_mask.h29657 #define SQ_WAVE_STATUS__VCCZ_MASK … macro
H A Dgc_9_4_3_sh_mask.h31342 #define SQ_WAVE_STATUS__VCCZ_MASK … macro
H A Dgc_9_4_2_sh_mask.h32714 #define SQ_WAVE_STATUS__VCCZ_MASK … macro
H A Dgc_11_0_0_sh_mask.h41463 #define SQ_WAVE_STATUS__VCCZ_MASK … macro
H A Dgc_11_0_3_sh_mask.h44500 #define SQ_WAVE_STATUS__VCCZ_MASK … macro
H A Dgc_10_1_0_sh_mask.h42758 #define SQ_WAVE_STATUS__VCCZ_MASK … macro
H A Dgc_10_3_0_sh_mask.h48001 #define SQ_WAVE_STATUS__VCCZ_MASK … macro