Home
last modified time | relevance | path

Searched refs:SQ_WAVE_STATUS__VALID_MASK (Results 1 – 13 of 13) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h10002 #define SQ_WAVE_STATUS__VALID_MASK 0x00010000L macro
H A Dgfx_7_2_sh_mask.h12507 #define SQ_WAVE_STATUS__VALID_MASK 0x10000 macro
H A Dgfx_8_1_sh_mask.h14785 #define SQ_WAVE_STATUS__VALID_MASK 0x10000 macro
H A Dgfx_8_0_sh_mask.h14387 #define SQ_WAVE_STATUS__VALID_MASK 0x10000 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h28447 #define SQ_WAVE_STATUS__VALID_MASK … macro
H A Dgc_9_1_sh_mask.h29663 #define SQ_WAVE_STATUS__VALID_MASK … macro
H A Dgc_9_2_1_sh_mask.h29989 #define SQ_WAVE_STATUS__VALID_MASK … macro
H A Dgc_9_4_3_sh_mask.h31348 #define SQ_WAVE_STATUS__VALID_MASK … macro
H A Dgc_9_4_2_sh_mask.h32720 #define SQ_WAVE_STATUS__VALID_MASK … macro
H A Dgc_11_0_0_sh_mask.h41469 #define SQ_WAVE_STATUS__VALID_MASK … macro
H A Dgc_10_1_0_sh_mask.h42764 #define SQ_WAVE_STATUS__VALID_MASK … macro
H A Dgc_11_0_3_sh_mask.h44506 #define SQ_WAVE_STATUS__VALID_MASK … macro
H A Dgc_10_3_0_sh_mask.h48007 #define SQ_WAVE_STATUS__VALID_MASK … macro