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Searched refs:SQG_UTCL0_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK (Results 1 – 2 of 2) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_sh_mask.h7905 #define SQG_UTCL0_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK … macro
H A Dgc_10_3_0_sh_mask.h8224 #define SQG_UTCL0_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK … macro