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Searched refs:SPR_SR_ICE (Results 1 – 3 of 3) sorted by relevance

/openbmc/linux/arch/openrisc/include/asm/
H A Dprocessor.h25 #define KERNEL_SR (SPR_SR_DME | SPR_SR_IME | SPR_SR_ICE \
27 #define USER_SR (SPR_SR_DME | SPR_SR_IME | SPR_SR_ICE \
H A Dspr_defs.h219 #define SPR_SR_ICE 0x00000010 /* Instruction Cache Enable */ macro
/openbmc/linux/arch/openrisc/kernel/
H A Dhead.S43 #define EXCEPTION_SR (SPR_SR_DME | SPR_SR_IME | SPR_SR_DCE | SPR_SR_ICE | SPR_SR_SM)
44 #define SYSCALL_SR (SPR_SR_DME | SPR_SR_IME | SPR_SR_DCE | SPR_SR_ICE | SPR_SR_IEE | SPR_SR_TEE | …
837 l.xori r5,r5,SPR_SR_ICE
876 l.ori r6,r6,SPR_SR_ICE