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Searched refs:SPR_POWER_MMCR0 (Results 1 – 8 of 8) sorted by relevance

/openbmc/qemu/target/ppc/
H A Dpower8-pmu.c28 return env->spr[SPR_POWER_MMCR0] & MMCR0_PMC1CE; in pmc_has_overflow_enabled()
31 return env->spr[SPR_POWER_MMCR0] & MMCR0_PMCjCE; in pmc_has_overflow_enabled()
40 target_ulong mmcr0 = env->spr[SPR_POWER_MMCR0]; in pmu_update_summaries()
89 if (!(env->spr[SPR_POWER_MMCR0] & MMCR0_PMAE)) { in hreg_bhrb_filter_update()
123 if (env->spr[SPR_POWER_MMCR0] & MMCR0_PMAO) { in pmu_mmcr01a_updated()
139 target_ulong mmcr0 = env->spr[SPR_POWER_MMCR0]; in pmu_increment_insns()
294 env->spr[SPR_POWER_MMCR0] = value; in helper_store_mmcr0()
341 env->spr[SPR_POWER_MMCR0] |= MMCR0_FC; in perfm_alert()
354 if (env->spr[SPR_POWER_MMCR0] & MMCR0_PMAE) { in perfm_alert()
356 env->spr[SPR_POWER_MMCR0] &= ~MMCR0_PMAE; in perfm_alert()
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H A Dhelper_regs.c65 mmcr0 = env->spr[SPR_POWER_MMCR0]; in hreg_check_bhrb_enable()
88 if (env->spr[SPR_POWER_MMCR0] & MMCR0_PMCC0) { in hreg_compute_pmu_hflags_value()
91 if (env->spr[SPR_POWER_MMCR0] & MMCR0_PMCC1) { in hreg_compute_pmu_hflags_value()
94 if (env->spr[SPR_POWER_MMCR0] & MMCR0_PMCjCE) { in hreg_compute_pmu_hflags_value()
H A Dmisc_helper.c157 !(env->spr[SPR_POWER_MMCR0] & (1ULL << bit))) { in helper_mmcr0_facility_check()
482 (env->spr[SPR_POWER_MMCR0] & MMCR0_PMAE)) { in helper_mfbhrbe()
H A Dpower8-pmu-regs.c.inc96 gen_load_spr(t0, SPR_POWER_MMCR0);
131 masked_gprn = masked_gprn_for_spr_write(gprn, SPR_POWER_MMCR0,
H A Dcpu.h2058 #define SPR_POWER_MMCR0 (0X31B) macro
H A Dexcp_helper.c2745 bool perfm_ebb_enabled = env->spr[SPR_POWER_MMCR0] & MMCR0_EBE && in raise_ebb_perfm_exception()
H A Dcpu_init.c5185 spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0", in register_book3s_pmu_sup_sprs()
/openbmc/qemu/hw/ppc/
H A Dspapr_nested.c206 save->mmcr0 = env->spr[SPR_POWER_MMCR0]; in nested_save_state()
305 env->spr[SPR_POWER_MMCR0] = load->mmcr0; in nested_load_state()