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Searched refs:SPR_40x_TSR (Results 1 – 3 of 3) sorted by relevance

/openbmc/qemu/hw/ppc/
H A Dppc.c1212 env->spr[SPR_40x_TSR] |= 1 << 26; in cpu_4xx_fit_cb()
1217 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]); in cpu_4xx_fit_cb()
1257 env->spr[SPR_40x_TSR] |= 1 << 27; in cpu_4xx_pit_cb()
1264 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR], in cpu_4xx_pit_cb()
1298 trace_ppc4xx_wdt(env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]); in cpu_4xx_wdt_cb()
1299 switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) { in cpu_4xx_wdt_cb()
1304 env->spr[SPR_40x_TSR] |= 1U << 31; in cpu_4xx_wdt_cb()
1309 env->spr[SPR_40x_TSR] |= 1 << 30; in cpu_4xx_wdt_cb()
1315 env->spr[SPR_40x_TSR] &= ~0x30000000; in cpu_4xx_wdt_cb()
1316 env->spr[SPR_40x_TSR] |= env->spr[SPR_40x_TCR] & 0x30000000; in cpu_4xx_wdt_cb()
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/openbmc/qemu/target/ppc/
H A Dcpu.h2208 #define SPR_40x_TSR (0x3D8) macro
H A Dcpu_init.c1138 spr_register(env, SPR_40x_TSR, "TSR", in register_40x_sprs()
7718 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR], in ppc_cpu_dump_state()