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Searched refs:SPRN_L1CSR2 (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/arch/powerpc/include/asm/
H A Dprocessor.h497 #define SPRN_L1CSR2 0x25e /* L1 Data Cache Control and Status Register 2 */ macro
735 #define L1CSR2 SPRN_L1CSR2
/openbmc/linux/arch/powerpc/include/asm/
H A Dreg_booke.h144 #define SPRN_L1CSR2 0x25E /* L1 Cache Control and Status Register 2 */ macro
/openbmc/linux/arch/powerpc/kernel/
H A Dtraps.c656 if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS)) in machine_check_e500mc()