1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2016 Freescale Semiconductor 4 */ 5 6 #ifndef __LS1046A_COMMON_H 7 #define __LS1046A_COMMON_H 8 9 /* SPL build */ 10 #ifdef CONFIG_SPL_BUILD 11 #define SPL_NO_QBMAN 12 #define SPL_NO_FMAN 13 #define SPL_NO_ENV 14 #define SPL_NO_MISC 15 #define SPL_NO_QSPI 16 #define SPL_NO_USB 17 #define SPL_NO_SATA 18 #endif 19 #if defined(CONFIG_SPL_BUILD) && \ 20 (defined(CONFIG_NAND_BOOT) || defined(CONFIG_QSPI_BOOT)) 21 #define SPL_NO_MMC 22 #endif 23 #if defined(CONFIG_SPL_BUILD) && \ 24 !defined(CONFIG_SPL_FSL_LS_PPA) 25 #define SPL_NO_IFC 26 #endif 27 28 #define CONFIG_REMAKE_ELF 29 #define CONFIG_GICV2 30 31 #include <asm/arch/config.h> 32 #include <asm/arch/stream_id_lsch2.h> 33 34 /* Link Definitions */ 35 #ifdef CONFIG_TFABOOT 36 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE 37 #else 38 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) 39 #endif 40 41 #define CONFIG_SKIP_LOWLEVEL_INIT 42 43 #define CONFIG_VERY_BIG_RAM 44 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 45 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 46 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 47 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL 48 49 #define CPU_RELEASE_ADDR secondary_boot_func 50 51 /* Generic Timer Definitions */ 52 #define COUNTER_FREQUENCY 25000000 /* 25MHz */ 53 54 /* Size of malloc() pool */ 55 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) 56 57 /* Serial Port */ 58 #define CONFIG_SYS_NS16550_SERIAL 59 #define CONFIG_SYS_NS16550_REG_SIZE 1 60 #define CONFIG_SYS_NS16550_CLK (get_serial_clock()) 61 62 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 63 64 /* SD boot SPL */ 65 #ifdef CONFIG_SD_BOOT 66 #define CONFIG_SPL_TEXT_BASE 0x10000000 67 #define CONFIG_SPL_MAX_SIZE 0x1f000 /* 124 KiB */ 68 #define CONFIG_SPL_STACK 0x10020000 69 #define CONFIG_SPL_PAD_TO 0x21000 /* 132 KiB */ 70 #define CONFIG_SPL_BSS_START_ADDR 0x8f000000 71 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 72 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ 73 CONFIG_SPL_BSS_MAX_SIZE) 74 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 75 76 #ifdef CONFIG_SECURE_BOOT 77 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) 78 /* 79 * HDR would be appended at end of image and copied to DDR along 80 * with U-Boot image. Here u-boot max. size is 512K. So if binary 81 * size increases then increase this size in case of secure boot as 82 * it uses raw u-boot image instead of fit image. 83 */ 84 #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) 85 #else 86 #define CONFIG_SYS_MONITOR_LEN 0x100000 87 #endif /* ifdef CONFIG_SECURE_BOOT */ 88 #endif 89 90 #if defined(CONFIG_QSPI_BOOT) && defined(CONFIG_SPL) 91 #define CONFIG_SPL_TARGET "spl/u-boot-spl.pbl" 92 #define CONFIG_SPL_TEXT_BASE 0x10000000 93 #define CONFIG_SPL_MAX_SIZE 0x1f000 94 #define CONFIG_SPL_STACK 0x10020000 95 #define CONFIG_SPL_PAD_TO 0x20000 96 #define CONFIG_SPL_BSS_START_ADDR 0x8f000000 97 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 98 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ 99 CONFIG_SPL_BSS_MAX_SIZE) 100 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 101 #define CONFIG_SYS_MONITOR_LEN 0x100000 102 #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE 103 #endif 104 105 /* NAND SPL */ 106 #ifdef CONFIG_NAND_BOOT 107 #define CONFIG_SPL_PBL_PAD 108 #define CONFIG_SPL_LIBCOMMON_SUPPORT 109 #define CONFIG_SPL_LIBGENERIC_SUPPORT 110 #define CONFIG_SPL_ENV_SUPPORT 111 #define CONFIG_SPL_WATCHDOG_SUPPORT 112 #define CONFIG_SPL_I2C_SUPPORT 113 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 114 115 #define CONFIG_SPL_NAND_SUPPORT 116 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 117 #define CONFIG_SPL_TEXT_BASE 0x10000000 118 #define CONFIG_SPL_MAX_SIZE 0x17000 /* 90 KiB */ 119 #define CONFIG_SPL_STACK 0x1001f000 120 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 121 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 122 123 #define CONFIG_SPL_BSS_START_ADDR 0x8f000000 124 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 125 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ 126 CONFIG_SPL_BSS_MAX_SIZE) 127 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 128 #define CONFIG_SYS_MONITOR_LEN 0xa0000 129 #endif 130 131 /* I2C */ 132 #define CONFIG_SYS_I2C 133 134 /* PCIe */ 135 #define CONFIG_PCIE1 /* PCIE controller 1 */ 136 #define CONFIG_PCIE2 /* PCIE controller 2 */ 137 #define CONFIG_PCIE3 /* PCIE controller 3 */ 138 139 #ifdef CONFIG_PCI 140 #define CONFIG_PCI_SCAN_SHOW 141 #endif 142 143 /* SATA */ 144 #ifndef SPL_NO_SATA 145 #define CONFIG_SCSI_AHCI_PLAT 146 147 #define CONFIG_SYS_SATA AHCI_BASE_ADDR 148 149 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 150 #define CONFIG_SYS_SCSI_MAX_LUN 1 151 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 152 CONFIG_SYS_SCSI_MAX_LUN) 153 #endif 154 155 /* Command line configuration */ 156 157 /* MMC */ 158 #ifndef SPL_NO_MMC 159 #ifdef CONFIG_MMC 160 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 161 #endif 162 #endif 163 164 /* FMan ucode */ 165 #ifndef SPL_NO_FMAN 166 #define CONFIG_SYS_DPAA_FMAN 167 #ifdef CONFIG_SYS_DPAA_FMAN 168 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 169 #endif 170 171 #ifdef CONFIG_TFABOOT 172 #define CONFIG_SYS_FMAN_FW_ADDR 0x900000 173 #else 174 #ifdef CONFIG_SD_BOOT 175 /* 176 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 177 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 178 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 18432(0x4800). 179 */ 180 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 181 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800) 182 #elif defined(CONFIG_QSPI_BOOT) 183 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 184 #define CONFIG_SYS_FMAN_FW_ADDR 0x40900000 185 #elif defined(CONFIG_NAND_BOOT) 186 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 187 #define CONFIG_SYS_FMAN_FW_ADDR (36 * CONFIG_SYS_NAND_BLOCK_SIZE) 188 #else 189 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 190 #define CONFIG_SYS_FMAN_FW_ADDR 0x60900000 191 #endif 192 #endif 193 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 194 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 195 #endif 196 197 /* Miscellaneous configurable options */ 198 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) 199 200 #define CONFIG_HWCONFIG 201 #define HWCONFIG_BUFFER_SIZE 128 202 203 #ifndef CONFIG_SPL_BUILD 204 #define BOOT_TARGET_DEVICES(func) \ 205 func(SCSI, scsi, 0) \ 206 func(MMC, mmc, 0) \ 207 func(USB, usb, 0) \ 208 func(DHCP, dhcp, na) 209 #include <config_distro_bootcmd.h> 210 #endif 211 212 #ifndef SPL_NO_MISC 213 /* Initial environment variables */ 214 #define CONFIG_EXTRA_ENV_SETTINGS \ 215 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 216 "ramdisk_addr=0x800000\0" \ 217 "ramdisk_size=0x2000000\0" \ 218 "fdt_high=0xffffffffffffffff\0" \ 219 "initrd_high=0xffffffffffffffff\0" \ 220 "fdt_addr=0x64f00000\0" \ 221 "kernel_addr=0x65000000\0" \ 222 "scriptaddr=0x80000000\0" \ 223 "scripthdraddr=0x80080000\0" \ 224 "fdtheader_addr_r=0x80100000\0" \ 225 "kernelheader_addr_r=0x80200000\0" \ 226 "load_addr=0xa0000000\0" \ 227 "kernel_addr_r=0x81000000\0" \ 228 "fdt_addr_r=0x90000000\0" \ 229 "ramdisk_addr_r=0xa0000000\0" \ 230 "kernel_start=0x1000000\0" \ 231 "kernelheader_start=0x800000\0" \ 232 "kernel_load=0xa0000000\0" \ 233 "kernel_size=0x2800000\0" \ 234 "kernelheader_size=0x40000\0" \ 235 "kernel_addr_sd=0x8000\0" \ 236 "kernel_size_sd=0x14000\0" \ 237 "kernelhdr_addr_sd=0x4000\0" \ 238 "kernelhdr_size_sd=0x10\0" \ 239 "console=ttyS0,115200\0" \ 240 CONFIG_MTDPARTS_DEFAULT "\0" \ 241 BOOTENV \ 242 "boot_scripts=ls1046ardb_boot.scr\0" \ 243 "boot_script_hdr=hdr_ls1046ardb_bs.out\0" \ 244 "scan_dev_for_boot_part=" \ 245 "part list ${devtype} ${devnum} devplist; " \ 246 "env exists devplist || setenv devplist 1; " \ 247 "for distro_bootpart in ${devplist}; do " \ 248 "if fstype ${devtype} " \ 249 "${devnum}:${distro_bootpart} " \ 250 "bootfstype; then " \ 251 "run scan_dev_for_boot; " \ 252 "fi; " \ 253 "done\0" \ 254 "boot_a_script=" \ 255 "load ${devtype} ${devnum}:${distro_bootpart} " \ 256 "${scriptaddr} ${prefix}${script}; " \ 257 "env exists secureboot && load ${devtype} " \ 258 "${devnum}:${distro_bootpart} " \ 259 "${scripthdraddr} ${prefix}${boot_script_hdr} " \ 260 "&& esbc_validate ${scripthdraddr};" \ 261 "source ${scriptaddr}\0" \ 262 "qspi_bootcmd=echo Trying load from qspi..;" \ 263 "sf probe && sf read $load_addr " \ 264 "$kernel_start $kernel_size; env exists secureboot " \ 265 "&& sf read $kernelheader_addr_r $kernelheader_start " \ 266 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ 267 "bootm $load_addr#$board\0" \ 268 "sd_bootcmd=echo Trying load from SD ..;" \ 269 "mmcinfo; mmc read $load_addr " \ 270 "$kernel_addr_sd $kernel_size_sd && " \ 271 "env exists secureboot && mmc read $kernelheader_addr_r " \ 272 "$kernelhdr_addr_sd $kernelhdr_size_sd " \ 273 " && esbc_validate ${kernelheader_addr_r};" \ 274 "bootm $load_addr#$board\0" 275 276 #endif 277 278 /* Monitor Command Prompt */ 279 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 280 281 #define CONFIG_SYS_MAXARGS 64 /* max command args */ 282 283 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 284 285 #include <asm/arch/soc.h> 286 287 #endif /* __LS1046A_COMMON_H */ 288