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Searched refs:SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT (Results 1 – 13 of 13) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h7687 #define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT 0x00000000 macro
H A Dgfx_7_2_sh_mask.h8720 #define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT 0x0 macro
H A Dgfx_8_0_sh_mask.h10322 #define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT 0x0 macro
H A Dgfx_8_1_sh_mask.h10720 #define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT 0x0 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h16345 #define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT … macro
H A Dgc_9_2_1_sh_mask.h17529 #define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT … macro
H A Dgc_9_1_sh_mask.h17654 #define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT … macro
H A Dgc_9_4_3_sh_mask.h19828 #define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT … macro
H A Dgc_9_4_2_sh_mask.h9778 #define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT … macro
H A Dgc_11_0_0_sh_mask.h21541 #define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT … macro
H A Dgc_11_0_3_sh_mask.h23871 #define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT … macro
H A Dgc_10_1_0_sh_mask.h23852 #define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT … macro
H A Dgc_10_3_0_sh_mask.h22026 #define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT … macro