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Searched refs:SPI_PS_IN_CONTROL__NUM_INTERP_MASK (Results 1 – 13 of 13) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h7686 #define SPI_PS_IN_CONTROL__NUM_INTERP_MASK 0x0000003fL macro
H A Dgfx_7_2_sh_mask.h8719 #define SPI_PS_IN_CONTROL__NUM_INTERP_MASK 0x3f macro
H A Dgfx_8_1_sh_mask.h10719 #define SPI_PS_IN_CONTROL__NUM_INTERP_MASK 0x3f macro
H A Dgfx_8_0_sh_mask.h10321 #define SPI_PS_IN_CONTROL__NUM_INTERP_MASK 0x3f macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h16350 #define SPI_PS_IN_CONTROL__NUM_INTERP_MASK … macro
H A Dgc_9_1_sh_mask.h17659 #define SPI_PS_IN_CONTROL__NUM_INTERP_MASK … macro
H A Dgc_9_2_1_sh_mask.h17534 #define SPI_PS_IN_CONTROL__NUM_INTERP_MASK … macro
H A Dgc_9_4_3_sh_mask.h19833 #define SPI_PS_IN_CONTROL__NUM_INTERP_MASK … macro
H A Dgc_9_4_2_sh_mask.h9782 #define SPI_PS_IN_CONTROL__NUM_INTERP_MASK … macro
H A Dgc_11_0_0_sh_mask.h21548 #define SPI_PS_IN_CONTROL__NUM_INTERP_MASK … macro
H A Dgc_10_1_0_sh_mask.h23858 #define SPI_PS_IN_CONTROL__NUM_INTERP_MASK … macro
H A Dgc_11_0_3_sh_mask.h23878 #define SPI_PS_IN_CONTROL__NUM_INTERP_MASK … macro
H A Dgc_10_3_0_sh_mask.h22032 #define SPI_PS_IN_CONTROL__NUM_INTERP_MASK … macro