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Searched refs:SPI_GFX_CNTL__RESET_COUNTS_MASK (Results 1 – 11 of 11) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_8_0_sh_mask.h10827 #define SPI_GFX_CNTL__RESET_COUNTS_MASK 0x1 macro
H A Dgfx_8_1_sh_mask.h11225 #define SPI_GFX_CNTL__RESET_COUNTS_MASK 0x1 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h4169 #define SPI_GFX_CNTL__RESET_COUNTS_MASK … macro
H A Dgc_9_2_1_sh_mask.h3568 #define SPI_GFX_CNTL__RESET_COUNTS_MASK … macro
H A Dgc_9_1_sh_mask.h3704 #define SPI_GFX_CNTL__RESET_COUNTS_MASK … macro
H A Dgc_9_4_3_sh_mask.h4403 #define SPI_GFX_CNTL__RESET_COUNTS_MASK … macro
H A Dgc_9_4_2_sh_mask.h24505 #define SPI_GFX_CNTL__RESET_COUNTS_MASK … macro
H A Dgc_11_0_0_sh_mask.h7281 #define SPI_GFX_CNTL__RESET_COUNTS_MASK … macro
H A Dgc_11_0_3_sh_mask.h8769 #define SPI_GFX_CNTL__RESET_COUNTS_MASK … macro
H A Dgc_10_1_0_sh_mask.h8426 #define SPI_GFX_CNTL__RESET_COUNTS_MASK … macro
H A Dgc_10_3_0_sh_mask.h8767 #define SPI_GFX_CNTL__RESET_COUNTS_MASK … macro