Searched refs:SPI_CTL_REG (Results 1 – 2 of 2) sorted by relevance
33 #define SPI_CTL_REG 0x08 /* control register */ macro145 case SPI_CTL_REG: in allwinner_a10_spi_get_regname()170 return s->regs[REG_INDEX(SPI_CTL_REG)] & SPI_CTL_EN; in allwinner_a10_spi_is_enabled()191 return (s->regs[REG_INDEX(SPI_CTL_REG)] & SPI_CTL_SS) >> SPI_CTL_SS_SHIFT; in allwinner_a10_spi_selected_channel()200 s->regs[REG_INDEX(SPI_CTL_REG)] = SPI_CTL_RESET; in allwinner_a10_spi_reset_hold()308 if (s->regs[REG_INDEX(SPI_CTL_REG)] & SPI_CTL_DHB) { in allwinner_a10_spi_flush_txfifo()330 s->regs[REG_INDEX(SPI_CTL_REG)] &= ~SPI_CTL_XCH; in allwinner_a10_spi_flush_txfifo()337 s->regs[REG_INDEX(SPI_CTL_REG)] &= ~SPI_CTL_XCH; in allwinner_a10_spi_flush_txfifo()383 case SPI_CTL_REG: in allwinner_a10_spi_read()409 return (s->regs[REG_INDEX(SPI_CTL_REG)] & SPI_CTL_SS_LEVEL) != 0; in allwinner_a10_spi_update_cs_level()[all …]
23 #define SPI_CTL_REG 0x000 macro123 setbits_be32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_POL_MASK); in bcm63xx_hsspi_set_mode()125 clrbits_be32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_POL_MASK); in bcm63xx_hsspi_set_mode()185 clrsetbits_be32(priv->regs + SPI_CTL_REG, clr, set); in bcm63xx_hsspi_activate_cs()191 clrsetbits_be32(priv->regs + SPI_CTL_REG, SPI_CTL_CS_POL_MASK, in bcm63xx_hsspi_deactivate_cs()390 setbits_be32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_GATE_MASK); in bcm63xx_hsspi_probe()393 priv->cs_pols = readl_be(priv->regs + SPI_CTL_REG) & in bcm63xx_hsspi_probe()