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Searched refs:SOR (Results 1 – 25 of 26) sorted by relevance

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/openbmc/linux/Documentation/devicetree/bindings/display/tegra/
H A Dnvidia,tegra124-sor.yaml7 title: NVIDIA Tegra SOR Output Encoder
14 The Serial Output Resource (SOR) can be used to drive HDMI, LVDS, eDP
71 description: index of the SOR interface
93 Each lane of the SOR, identified by the cell's index, is
115 - description: clock input for the SOR hardware
116 - description: SOR output clock
118 - description: reference clock for the SOR clock
121 - description: SOR pad output clock
137 - description: clock input for the SOR hardware
138 - description: SOR output clock
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/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Doutp.c67 case DCB_OUTPUT_TMDS : *type = SOR; return TMDS; in nvkm_outp_xlat()
68 case DCB_OUTPUT_LVDS : *type = SOR; return LVDS; in nvkm_outp_xlat()
69 case DCB_OUTPUT_DP : *type = SOR; return DP; in nvkm_outp_xlat()
162 ior = nvkm_ior_find(outp->disp, SOR, ffs(outp->info.or) - 1); in nvkm_outp_acquire()
247 link = (ior->type == SOR) ? outp->info.sorconf.link : 0; in nvkm_outp_init_route()
H A Dmcp77.c41 return nvkm_ior_new_(&mcp77_sor, disp, SOR, id, false); in mcp77_sor_new()
H A Dior.c29 [SOR] = "SOR",
H A Dgp100.c54 return nvkm_ior_new_(&gp100_sor, disp, SOR, id, hda & BIT(id)); in gp100_sor_new()
H A Dmcp89.c55 return nvkm_ior_new_(&mcp89_sor, disp, SOR, id, true); in mcp89_sor_new()
H A Dgm107.c81 return nvkm_ior_new_(&gm107_sor, disp, SOR, id, true); in gm107_sor_new()
H A Dga102.c119 return nvkm_ior_new_(&ga102_sor, disp, SOR, id, hda & BIT(id)); in ga102_sor_new()
H A Dg94.c180 if (ior->type != SOR) in g94_sor_war_update_sppll1()
305 return nvkm_ior_new_(&g94_sor, disp, SOR, id, false); in g94_sor_new()
H A Dgk104.c126 return nvkm_ior_new_(&gk104_sor, disp, SOR, id, true); in gk104_sor_new()
H A Dg84.c133 return nvkm_ior_new_(&g84_sor, disp, SOR, id, false); in g84_sor_new()
H A Dgm200.c156 return nvkm_ior_new_(&gm200_sor, disp, SOR, id, hda & BIT(id)); in gm200_sor_new()
H A Dtu102.c102 return nvkm_ior_new_(&tu102_sor, disp, SOR, id, hda & BIT(id)); in tu102_sor_new()
H A Dgt215.c198 return nvkm_ior_new_(&gt215_sor, disp, SOR, id, true); in gt215_sor_new()
H A Dior.h12 SOR, enumerator
H A Dnv50.c228 return nvkm_ior_new_(&nv50_sor, disp, SOR, id, false); in nv50_sor_new()
1017 if (ior->type == SOR) { in nv50_disp_super_ied_on()
1252 if (outp && ior->type == SOR && ior->asy.proto == LVDS) { in nv50_disp_super_2_2()
1268 if (ior->type == SOR && ior->asy.proto == DP) in nv50_disp_super_2_2()
H A Dbase.c291 ior = nvkm_ior_find(disp, SOR, ffs(outp->info.or) - 1); in nvkm_disp_oneinit()
H A Dgf119.c339 return nvkm_ior_new_(&gf119_sor, disp, SOR, id, true); in gf119_sor_new()
/openbmc/u-boot/arch/powerpc/cpu/mpc8xx/
H A Dimmap.c185 SOR, in do_iopset() enumerator
221 cmd = SOR; in do_iopset()
253 case SOR: in do_iopset()
/openbmc/linux/drivers/gpu/drm/nouveau/dispnv50/
H A Dcrcc57d.c26 crc_args |= NVDEF(NVC57D, HEAD_SET_CRC_CONTROL, PRIMARY_CRC, SOR(or)); in crcc57d_set_src()
H A Dcrcc37d.c28 crc_args |= NVDEF(NVC37D, HEAD_SET_CRC_CONTROL, PRIMARY_CRC, SOR(or)); in crcc37d_set_src()
H A Dcrc907d.c41 crc_args |= NVDEF(NV907D, HEAD_SET_CRC_CONTROL, PRIMARY_OUTPUT, SOR(or)); in crc907d_set_src()
/openbmc/linux/Documentation/gpu/
H A Dtegra.rst80 controllers can drive both DSI outputs and both SOR outputs, the third cannot
117 by the versatile SOR output, which supports eDP, DP and HDMI. The SOR is able
/openbmc/u-boot/doc/device-tree-bindings/gpu/
H A Dnvidia,tegra20-host1x.txt204 - sor: clock input for the SOR hardware
206 - dp: reference clock for the SOR clock
207 - safe: safe reference for the SOR clock during power up
/openbmc/u-boot/arch/arm/include/asm/arch-tegra/
H A Dpmc.h296 #define SOR 17 macro

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