1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * Copyright (C) 2014 Freescale Semiconductor, Inc.
4 */
5
6 #ifndef __LINUX_MTD_SPI_NOR_H
7 #define __LINUX_MTD_SPI_NOR_H
8
9 #include <linux/bitops.h>
10 #include <linux/mtd/mtd.h>
11 #include <linux/spi/spi-mem.h>
12
13 /*
14 * Note on opcode nomenclature: some opcodes have a format like
15 * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number
16 * of I/O lines used for the opcode, address, and data (respectively). The
17 * FUNCTION has an optional suffix of '4', to represent an opcode which
18 * requires a 4-byte (32-bit) address.
19 */
20
21 /* Flash opcodes. */
22 #define SPINOR_OP_WRDI 0x04 /* Write disable */
23 #define SPINOR_OP_WREN 0x06 /* Write enable */
24 #define SPINOR_OP_RDSR 0x05 /* Read status register */
25 #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */
26 #define SPINOR_OP_RDSR2 0x3f /* Read status register 2 */
27 #define SPINOR_OP_WRSR2 0x3e /* Write status register 2 */
28 #define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */
29 #define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */
30 #define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual Output SPI) */
31 #define SPINOR_OP_READ_1_2_2 0xbb /* Read data bytes (Dual I/O SPI) */
32 #define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */
33 #define SPINOR_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */
34 #define SPINOR_OP_READ_1_1_8 0x8b /* Read data bytes (Octal Output SPI) */
35 #define SPINOR_OP_READ_1_8_8 0xcb /* Read data bytes (Octal I/O SPI) */
36 #define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */
37 #define SPINOR_OP_PP_1_1_4 0x32 /* Quad page program */
38 #define SPINOR_OP_PP_1_4_4 0x38 /* Quad page program */
39 #define SPINOR_OP_PP_1_1_8 0x82 /* Octal page program */
40 #define SPINOR_OP_PP_1_8_8 0xc2 /* Octal page program */
41 #define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */
42 #define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
43 #define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */
44 #define SPINOR_OP_CHIP_ERASE 0xc7 /* Erase whole flash chip */
45 #define SPINOR_OP_SE 0xd8 /* Sector erase (usually 64KiB) */
46 #define SPINOR_OP_RDID 0x9f /* Read JEDEC ID */
47 #define SPINOR_OP_RDSFDP 0x5a /* Read SFDP */
48 #define SPINOR_OP_RDCR 0x35 /* Read configuration register */
49 #define SPINOR_OP_SRSTEN 0x66 /* Software Reset Enable */
50 #define SPINOR_OP_SRST 0x99 /* Software Reset */
51 #define SPINOR_OP_GBULK 0x98 /* Global Block Unlock */
52
53 /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
54 #define SPINOR_OP_READ_4B 0x13 /* Read data bytes (low frequency) */
55 #define SPINOR_OP_READ_FAST_4B 0x0c /* Read data bytes (high frequency) */
56 #define SPINOR_OP_READ_1_1_2_4B 0x3c /* Read data bytes (Dual Output SPI) */
57 #define SPINOR_OP_READ_1_2_2_4B 0xbc /* Read data bytes (Dual I/O SPI) */
58 #define SPINOR_OP_READ_1_1_4_4B 0x6c /* Read data bytes (Quad Output SPI) */
59 #define SPINOR_OP_READ_1_4_4_4B 0xec /* Read data bytes (Quad I/O SPI) */
60 #define SPINOR_OP_READ_1_1_8_4B 0x7c /* Read data bytes (Octal Output SPI) */
61 #define SPINOR_OP_READ_1_8_8_4B 0xcc /* Read data bytes (Octal I/O SPI) */
62 #define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */
63 #define SPINOR_OP_PP_1_1_4_4B 0x34 /* Quad page program */
64 #define SPINOR_OP_PP_1_4_4_4B 0x3e /* Quad page program */
65 #define SPINOR_OP_PP_1_1_8_4B 0x84 /* Octal page program */
66 #define SPINOR_OP_PP_1_8_8_4B 0x8e /* Octal page program */
67 #define SPINOR_OP_BE_4K_4B 0x21 /* Erase 4KiB block */
68 #define SPINOR_OP_BE_32K_4B 0x5c /* Erase 32KiB block */
69 #define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */
70
71 /* Double Transfer Rate opcodes - defined in JEDEC JESD216B. */
72 #define SPINOR_OP_READ_1_1_1_DTR 0x0d
73 #define SPINOR_OP_READ_1_2_2_DTR 0xbd
74 #define SPINOR_OP_READ_1_4_4_DTR 0xed
75
76 #define SPINOR_OP_READ_1_1_1_DTR_4B 0x0e
77 #define SPINOR_OP_READ_1_2_2_DTR_4B 0xbe
78 #define SPINOR_OP_READ_1_4_4_DTR_4B 0xee
79
80 /* Used for SST flashes only. */
81 #define SPINOR_OP_BP 0x02 /* Byte program */
82 #define SPINOR_OP_AAI_WP 0xad /* Auto address increment word program */
83
84 /* Used for Macronix and Winbond flashes. */
85 #define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */
86 #define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */
87
88 /* Used for Spansion flashes only. */
89 #define SPINOR_OP_BRWR 0x17 /* Bank register write */
90
91 /* Used for Micron flashes only. */
92 #define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */
93 #define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */
94
95 /* Used for GigaDevices and Winbond flashes. */
96 #define SPINOR_OP_ESECR 0x44 /* Erase Security registers */
97 #define SPINOR_OP_PSECR 0x42 /* Program Security registers */
98 #define SPINOR_OP_RSECR 0x48 /* Read Security registers */
99
100 /* Status Register bits. */
101 #define SR_WIP BIT(0) /* Write in progress */
102 #define SR_WEL BIT(1) /* Write enable latch */
103 /* meaning of other SR_* bits may differ between vendors */
104 #define SR_BP0 BIT(2) /* Block protect 0 */
105 #define SR_BP1 BIT(3) /* Block protect 1 */
106 #define SR_BP2 BIT(4) /* Block protect 2 */
107 #define SR_BP3 BIT(5) /* Block protect 3 */
108 #define SR_TB_BIT5 BIT(5) /* Top/Bottom protect */
109 #define SR_BP3_BIT6 BIT(6) /* Block protect 3 */
110 #define SR_TB_BIT6 BIT(6) /* Top/Bottom protect */
111 #define SR_SRWD BIT(7) /* SR write protect */
112 /* Spansion/Cypress specific status bits */
113 #define SR_E_ERR BIT(5)
114 #define SR_P_ERR BIT(6)
115
116 #define SR1_QUAD_EN_BIT6 BIT(6)
117
118 #define SR_BP_SHIFT 2
119
120 /* Enhanced Volatile Configuration Register bits */
121 #define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */
122
123 /* Status Register 2 bits. */
124 #define SR2_QUAD_EN_BIT1 BIT(1)
125 #define SR2_LB1 BIT(3) /* Security Register Lock Bit 1 */
126 #define SR2_LB2 BIT(4) /* Security Register Lock Bit 2 */
127 #define SR2_LB3 BIT(5) /* Security Register Lock Bit 3 */
128 #define SR2_QUAD_EN_BIT7 BIT(7)
129
130 /* Supported SPI protocols */
131 #define SNOR_PROTO_INST_MASK GENMASK(23, 16)
132 #define SNOR_PROTO_INST_SHIFT 16
133 #define SNOR_PROTO_INST(_nbits) \
134 ((((unsigned long)(_nbits)) << SNOR_PROTO_INST_SHIFT) & \
135 SNOR_PROTO_INST_MASK)
136
137 #define SNOR_PROTO_ADDR_MASK GENMASK(15, 8)
138 #define SNOR_PROTO_ADDR_SHIFT 8
139 #define SNOR_PROTO_ADDR(_nbits) \
140 ((((unsigned long)(_nbits)) << SNOR_PROTO_ADDR_SHIFT) & \
141 SNOR_PROTO_ADDR_MASK)
142
143 #define SNOR_PROTO_DATA_MASK GENMASK(7, 0)
144 #define SNOR_PROTO_DATA_SHIFT 0
145 #define SNOR_PROTO_DATA(_nbits) \
146 ((((unsigned long)(_nbits)) << SNOR_PROTO_DATA_SHIFT) & \
147 SNOR_PROTO_DATA_MASK)
148
149 #define SNOR_PROTO_IS_DTR BIT(24) /* Double Transfer Rate */
150
151 #define SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits) \
152 (SNOR_PROTO_INST(_inst_nbits) | \
153 SNOR_PROTO_ADDR(_addr_nbits) | \
154 SNOR_PROTO_DATA(_data_nbits))
155 #define SNOR_PROTO_DTR(_inst_nbits, _addr_nbits, _data_nbits) \
156 (SNOR_PROTO_IS_DTR | \
157 SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits))
158
159 enum spi_nor_protocol {
160 SNOR_PROTO_1_1_1 = SNOR_PROTO_STR(1, 1, 1),
161 SNOR_PROTO_1_1_2 = SNOR_PROTO_STR(1, 1, 2),
162 SNOR_PROTO_1_1_4 = SNOR_PROTO_STR(1, 1, 4),
163 SNOR_PROTO_1_1_8 = SNOR_PROTO_STR(1, 1, 8),
164 SNOR_PROTO_1_2_2 = SNOR_PROTO_STR(1, 2, 2),
165 SNOR_PROTO_1_4_4 = SNOR_PROTO_STR(1, 4, 4),
166 SNOR_PROTO_1_8_8 = SNOR_PROTO_STR(1, 8, 8),
167 SNOR_PROTO_2_2_2 = SNOR_PROTO_STR(2, 2, 2),
168 SNOR_PROTO_4_4_4 = SNOR_PROTO_STR(4, 4, 4),
169 SNOR_PROTO_8_8_8 = SNOR_PROTO_STR(8, 8, 8),
170
171 SNOR_PROTO_1_1_1_DTR = SNOR_PROTO_DTR(1, 1, 1),
172 SNOR_PROTO_1_2_2_DTR = SNOR_PROTO_DTR(1, 2, 2),
173 SNOR_PROTO_1_4_4_DTR = SNOR_PROTO_DTR(1, 4, 4),
174 SNOR_PROTO_1_8_8_DTR = SNOR_PROTO_DTR(1, 8, 8),
175 SNOR_PROTO_8_8_8_DTR = SNOR_PROTO_DTR(8, 8, 8),
176 };
177
spi_nor_protocol_is_dtr(enum spi_nor_protocol proto)178 static inline bool spi_nor_protocol_is_dtr(enum spi_nor_protocol proto)
179 {
180 return !!(proto & SNOR_PROTO_IS_DTR);
181 }
182
spi_nor_get_protocol_inst_nbits(enum spi_nor_protocol proto)183 static inline u8 spi_nor_get_protocol_inst_nbits(enum spi_nor_protocol proto)
184 {
185 return ((unsigned long)(proto & SNOR_PROTO_INST_MASK)) >>
186 SNOR_PROTO_INST_SHIFT;
187 }
188
spi_nor_get_protocol_addr_nbits(enum spi_nor_protocol proto)189 static inline u8 spi_nor_get_protocol_addr_nbits(enum spi_nor_protocol proto)
190 {
191 return ((unsigned long)(proto & SNOR_PROTO_ADDR_MASK)) >>
192 SNOR_PROTO_ADDR_SHIFT;
193 }
194
spi_nor_get_protocol_data_nbits(enum spi_nor_protocol proto)195 static inline u8 spi_nor_get_protocol_data_nbits(enum spi_nor_protocol proto)
196 {
197 return ((unsigned long)(proto & SNOR_PROTO_DATA_MASK)) >>
198 SNOR_PROTO_DATA_SHIFT;
199 }
200
spi_nor_get_protocol_width(enum spi_nor_protocol proto)201 static inline u8 spi_nor_get_protocol_width(enum spi_nor_protocol proto)
202 {
203 return spi_nor_get_protocol_data_nbits(proto);
204 }
205
206 /**
207 * struct spi_nor_hwcaps - Structure for describing the hardware capabilies
208 * supported by the SPI controller (bus master).
209 * @mask: the bitmask listing all the supported hw capabilies
210 */
211 struct spi_nor_hwcaps {
212 u32 mask;
213 };
214
215 /*
216 *(Fast) Read capabilities.
217 * MUST be ordered by priority: the higher bit position, the higher priority.
218 * As a matter of performances, it is relevant to use Octal SPI protocols first,
219 * then Quad SPI protocols before Dual SPI protocols, Fast Read and lastly
220 * (Slow) Read.
221 */
222 #define SNOR_HWCAPS_READ_MASK GENMASK(15, 0)
223 #define SNOR_HWCAPS_READ BIT(0)
224 #define SNOR_HWCAPS_READ_FAST BIT(1)
225 #define SNOR_HWCAPS_READ_1_1_1_DTR BIT(2)
226
227 #define SNOR_HWCAPS_READ_DUAL GENMASK(6, 3)
228 #define SNOR_HWCAPS_READ_1_1_2 BIT(3)
229 #define SNOR_HWCAPS_READ_1_2_2 BIT(4)
230 #define SNOR_HWCAPS_READ_2_2_2 BIT(5)
231 #define SNOR_HWCAPS_READ_1_2_2_DTR BIT(6)
232
233 #define SNOR_HWCAPS_READ_QUAD GENMASK(10, 7)
234 #define SNOR_HWCAPS_READ_1_1_4 BIT(7)
235 #define SNOR_HWCAPS_READ_1_4_4 BIT(8)
236 #define SNOR_HWCAPS_READ_4_4_4 BIT(9)
237 #define SNOR_HWCAPS_READ_1_4_4_DTR BIT(10)
238
239 #define SNOR_HWCAPS_READ_OCTAL GENMASK(15, 11)
240 #define SNOR_HWCAPS_READ_1_1_8 BIT(11)
241 #define SNOR_HWCAPS_READ_1_8_8 BIT(12)
242 #define SNOR_HWCAPS_READ_8_8_8 BIT(13)
243 #define SNOR_HWCAPS_READ_1_8_8_DTR BIT(14)
244 #define SNOR_HWCAPS_READ_8_8_8_DTR BIT(15)
245
246 /*
247 * Page Program capabilities.
248 * MUST be ordered by priority: the higher bit position, the higher priority.
249 * Like (Fast) Read capabilities, Octal/Quad SPI protocols are preferred to the
250 * legacy SPI 1-1-1 protocol.
251 * Note that Dual Page Programs are not supported because there is no existing
252 * JEDEC/SFDP standard to define them. Also at this moment no SPI flash memory
253 * implements such commands.
254 */
255 #define SNOR_HWCAPS_PP_MASK GENMASK(23, 16)
256 #define SNOR_HWCAPS_PP BIT(16)
257
258 #define SNOR_HWCAPS_PP_QUAD GENMASK(19, 17)
259 #define SNOR_HWCAPS_PP_1_1_4 BIT(17)
260 #define SNOR_HWCAPS_PP_1_4_4 BIT(18)
261 #define SNOR_HWCAPS_PP_4_4_4 BIT(19)
262
263 #define SNOR_HWCAPS_PP_OCTAL GENMASK(23, 20)
264 #define SNOR_HWCAPS_PP_1_1_8 BIT(20)
265 #define SNOR_HWCAPS_PP_1_8_8 BIT(21)
266 #define SNOR_HWCAPS_PP_8_8_8 BIT(22)
267 #define SNOR_HWCAPS_PP_8_8_8_DTR BIT(23)
268
269 #define SNOR_HWCAPS_X_X_X (SNOR_HWCAPS_READ_2_2_2 | \
270 SNOR_HWCAPS_READ_4_4_4 | \
271 SNOR_HWCAPS_READ_8_8_8 | \
272 SNOR_HWCAPS_PP_4_4_4 | \
273 SNOR_HWCAPS_PP_8_8_8)
274
275 #define SNOR_HWCAPS_X_X_X_DTR (SNOR_HWCAPS_READ_8_8_8_DTR | \
276 SNOR_HWCAPS_PP_8_8_8_DTR)
277
278 #define SNOR_HWCAPS_DTR (SNOR_HWCAPS_READ_1_1_1_DTR | \
279 SNOR_HWCAPS_READ_1_2_2_DTR | \
280 SNOR_HWCAPS_READ_1_4_4_DTR | \
281 SNOR_HWCAPS_READ_1_8_8_DTR | \
282 SNOR_HWCAPS_READ_8_8_8_DTR)
283
284 #define SNOR_HWCAPS_ALL (SNOR_HWCAPS_READ_MASK | \
285 SNOR_HWCAPS_PP_MASK)
286
287 /* Forward declaration that is used in 'struct spi_nor_controller_ops' */
288 struct spi_nor;
289
290 /**
291 * struct spi_nor_controller_ops - SPI NOR controller driver specific
292 * operations.
293 * @prepare: [OPTIONAL] do some preparations for the
294 * read/write/erase/lock/unlock operations.
295 * @unprepare: [OPTIONAL] do some post work after the
296 * read/write/erase/lock/unlock operations.
297 * @read_reg: read out the register.
298 * @write_reg: write data to the register.
299 * @read: read data from the SPI NOR.
300 * @write: write data to the SPI NOR.
301 * @erase: erase a sector of the SPI NOR at the offset @offs; if
302 * not provided by the driver, SPI NOR will send the erase
303 * opcode via write_reg().
304 */
305 struct spi_nor_controller_ops {
306 int (*prepare)(struct spi_nor *nor);
307 void (*unprepare)(struct spi_nor *nor);
308 int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, size_t len);
309 int (*write_reg)(struct spi_nor *nor, u8 opcode, const u8 *buf,
310 size_t len);
311
312 ssize_t (*read)(struct spi_nor *nor, loff_t from, size_t len, u8 *buf);
313 ssize_t (*write)(struct spi_nor *nor, loff_t to, size_t len,
314 const u8 *buf);
315 int (*erase)(struct spi_nor *nor, loff_t offs);
316 };
317
318 /**
319 * enum spi_nor_cmd_ext - describes the command opcode extension in DTR mode
320 * @SPI_NOR_EXT_NONE: no extension. This is the default, and is used in Legacy
321 * SPI mode
322 * @SPI_NOR_EXT_REPEAT: the extension is same as the opcode
323 * @SPI_NOR_EXT_INVERT: the extension is the bitwise inverse of the opcode
324 * @SPI_NOR_EXT_HEX: the extension is any hex value. The command and opcode
325 * combine to form a 16-bit opcode.
326 */
327 enum spi_nor_cmd_ext {
328 SPI_NOR_EXT_NONE = 0,
329 SPI_NOR_EXT_REPEAT,
330 SPI_NOR_EXT_INVERT,
331 SPI_NOR_EXT_HEX,
332 };
333
334 /*
335 * Forward declarations that are used internally by the core and manufacturer
336 * drivers.
337 */
338 struct flash_info;
339 struct spi_nor_manufacturer;
340 struct spi_nor_flash_parameter;
341
342 /**
343 * struct spi_nor - Structure for defining the SPI NOR layer
344 * @mtd: an mtd_info structure
345 * @lock: the lock for the read/write/erase/lock/unlock operations
346 * @rww: Read-While-Write (RWW) sync lock
347 * @rww.wait: wait queue for the RWW sync
348 * @rww.ongoing_io: the bus is busy
349 * @rww.ongoing_rd: a read is ongoing on the chip
350 * @rww.ongoing_pe: a program/erase is ongoing on the chip
351 * @rww.used_banks: bitmap of the banks in use
352 * @dev: pointer to an SPI device or an SPI NOR controller device
353 * @spimem: pointer to the SPI memory device
354 * @bouncebuf: bounce buffer used when the buffer passed by the MTD
355 * layer is not DMA-able
356 * @bouncebuf_size: size of the bounce buffer
357 * @id: The flash's ID bytes. Always contains
358 * SPI_NOR_MAX_ID_LEN bytes.
359 * @info: SPI NOR part JEDEC MFR ID and other info
360 * @manufacturer: SPI NOR manufacturer
361 * @addr_nbytes: number of address bytes
362 * @erase_opcode: the opcode for erasing a sector
363 * @read_opcode: the read opcode
364 * @read_dummy: the dummy needed by the read operation
365 * @program_opcode: the program opcode
366 * @sst_write_second: used by the SST write operation
367 * @flags: flag options for the current SPI NOR (SNOR_F_*)
368 * @cmd_ext_type: the command opcode extension type for DTR mode.
369 * @read_proto: the SPI protocol for read operations
370 * @write_proto: the SPI protocol for write operations
371 * @reg_proto: the SPI protocol for read_reg/write_reg/erase operations
372 * @sfdp: the SFDP data of the flash
373 * @debugfs_root: pointer to the debugfs directory
374 * @controller_ops: SPI NOR controller driver specific operations.
375 * @params: [FLASH-SPECIFIC] SPI NOR flash parameters and settings.
376 * The structure includes legacy flash parameters and
377 * settings that can be overwritten by the spi_nor_fixups
378 * hooks, or dynamically when parsing the SFDP tables.
379 * @dirmap: pointers to struct spi_mem_dirmap_desc for reads/writes.
380 * @priv: pointer to the private data
381 */
382 struct spi_nor {
383 struct mtd_info mtd;
384 struct mutex lock;
385 struct spi_nor_rww {
386 wait_queue_head_t wait;
387 bool ongoing_io;
388 bool ongoing_rd;
389 bool ongoing_pe;
390 unsigned int used_banks;
391 } rww;
392 struct device *dev;
393 struct spi_mem *spimem;
394 u8 *bouncebuf;
395 size_t bouncebuf_size;
396 u8 *id;
397 const struct flash_info *info;
398 const struct spi_nor_manufacturer *manufacturer;
399 u8 addr_nbytes;
400 u8 erase_opcode;
401 u8 read_opcode;
402 u8 read_dummy;
403 u8 program_opcode;
404 enum spi_nor_protocol read_proto;
405 enum spi_nor_protocol write_proto;
406 enum spi_nor_protocol reg_proto;
407 bool sst_write_second;
408 u32 flags;
409 enum spi_nor_cmd_ext cmd_ext_type;
410 struct sfdp *sfdp;
411 struct dentry *debugfs_root;
412
413 const struct spi_nor_controller_ops *controller_ops;
414
415 struct spi_nor_flash_parameter *params;
416
417 struct {
418 struct spi_mem_dirmap_desc *rdesc;
419 struct spi_mem_dirmap_desc *wdesc;
420 } dirmap;
421
422 void *priv;
423 };
424
spi_nor_set_flash_node(struct spi_nor * nor,struct device_node * np)425 static inline void spi_nor_set_flash_node(struct spi_nor *nor,
426 struct device_node *np)
427 {
428 mtd_set_of_node(&nor->mtd, np);
429 }
430
spi_nor_get_flash_node(struct spi_nor * nor)431 static inline struct device_node *spi_nor_get_flash_node(struct spi_nor *nor)
432 {
433 return mtd_get_of_node(&nor->mtd);
434 }
435
436 /**
437 * spi_nor_scan() - scan the SPI NOR
438 * @nor: the spi_nor structure
439 * @name: the chip type name
440 * @hwcaps: the hardware capabilities supported by the controller driver
441 *
442 * The drivers can use this function to scan the SPI NOR.
443 * In the scanning, it will try to get all the necessary information to
444 * fill the mtd_info{} and the spi_nor{}.
445 *
446 * The chip type name can be provided through the @name parameter.
447 *
448 * Return: 0 for success, others for failure.
449 */
450 int spi_nor_scan(struct spi_nor *nor, const char *name,
451 const struct spi_nor_hwcaps *hwcaps);
452
453 #endif
454