Searched refs:SMU_SCLK_DPM_STATE_0_CNTL_0 (Results 1 – 3 of 3) sorted by relevance
28 #define TRINITY_SIZEOF_DPM_STATE_TABLE (SMU_SCLK_DPM_STATE_1_CNTL_0 - SMU_SCLK_DPM_STATE_0_CNTL_0)
34 #define SMU_SCLK_DPM_STATE_0_CNTL_0 0x1f000 macro
552 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix); in trinity_set_divider_value()555 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value); in trinity_set_divider_value()599 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix); in trinity_set_vid()602 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value); in trinity_set_vid()604 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix); in trinity_set_vid()607 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value); in trinity_set_vid()695 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix); in trinity_power_level_enable_disable()699 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value); in trinity_power_level_enable_disable()