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Searched refs:SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE__SHIFT (Results 1 – 16 of 16) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_8_0_sh_mask.h1482 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE__SHIFT 0x0 macro
H A Ddce_10_0_sh_mask.h1512 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE__SHIFT 0x0 macro
H A Ddce_11_0_sh_mask.h1420 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE__SHIFT 0x0 macro
H A Ddce_11_2_sh_mask.h1548 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE__SHIFT 0x0 macro
H A Ddce_12_0_sh_mask.h2604 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE__SHIFT … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_sh_mask.h1306 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE__SHIFT … macro
H A Ddcn_2_1_0_sh_mask.h2104 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE__SHIFT … macro
H A Ddcn_3_2_1_sh_mask.h2760 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE__SHIFT … macro
H A Ddcn_1_0_sh_mask.h3603 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE__SHIFT … macro
H A Ddcn_3_1_2_sh_mask.h5583 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE__SHIFT … macro
H A Ddcn_3_1_6_sh_mask.h6180 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE__SHIFT … macro
H A Ddcn_3_0_2_sh_mask.h2175 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE__SHIFT … macro
H A Ddcn_3_1_4_sh_mask.h10342 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE__SHIFT … macro
H A Ddcn_3_0_0_sh_mask.h2242 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE__SHIFT … macro
H A Ddcn_2_0_0_sh_mask.h2372 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE__SHIFT … macro
H A Ddcn_3_2_0_sh_mask.h2761 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE__SHIFT … macro