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Searched refs:SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE_MASK (Results 1 – 16 of 16) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_8_0_sh_mask.h1481 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE_MASK 0x1 macro
H A Ddce_10_0_sh_mask.h1511 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE_MASK 0x1 macro
H A Ddce_11_0_sh_mask.h1419 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE_MASK 0x1 macro
H A Ddce_11_2_sh_mask.h1547 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE_MASK 0x1 macro
H A Ddce_12_0_sh_mask.h2607 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE_MASK … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_sh_mask.h1309 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE_MASK … macro
H A Ddcn_2_1_0_sh_mask.h2107 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE_MASK … macro
H A Ddcn_3_2_1_sh_mask.h2763 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE_MASK … macro
H A Ddcn_1_0_sh_mask.h3606 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE_MASK … macro
H A Ddcn_3_1_2_sh_mask.h5586 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE_MASK … macro
H A Ddcn_3_1_6_sh_mask.h6183 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE_MASK … macro
H A Ddcn_3_0_2_sh_mask.h2178 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE_MASK … macro
H A Ddcn_3_1_4_sh_mask.h10345 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE_MASK … macro
H A Ddcn_3_0_0_sh_mask.h2245 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE_MASK … macro
H A Ddcn_2_0_0_sh_mask.h2375 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE_MASK … macro
H A Ddcn_3_2_0_sh_mask.h2764 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE_MASK … macro