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Searched refs:SMSTATEEN0_P1P13 (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dcpu_bits.h320 #define SMSTATEEN0_P1P13 (1ULL << 56) macro
H A Dcsr.c2503 wr_mask |= SMSTATEEN0_P1P13; in write_mstateen0()
2542 wr_mask |= SMSTATEEN0_P1P13; in write_mstateen0h()
3487 ret = smstateen_acc_ok(env, 0, SMSTATEEN0_P1P13); in read_hedelegh()
3501 ret = smstateen_acc_ok(env, 0, SMSTATEEN0_P1P13); in write_hedelegh()