| /openbmc/linux/Documentation/i2c/ |
| H A D | functionality.rst | 2 I2C/SMBus Functionality
8 Because not every I2C or SMBus adapter implements everything in the
22 I2C_FUNC_I2C Plain i2c-level commands (Pure SMBus
30 I2C_FUNC_SMBUS_READ_BYTE Handles the SMBus read_byte command
46 I2C_FUNC_SMBUS_BYTE Handles the SMBus read_byte
48 I2C_FUNC_SMBUS_BYTE_DATA Handles the SMBus read_byte_data
50 I2C_FUNC_SMBUS_WORD_DATA Handles the SMBus read_word_data
52 I2C_FUNC_SMBUS_BLOCK_DATA Handles the SMBus read_block_data
72 A typical SMBus-only adapter would list all the SMBus transactions it
90 I2C_FUNC_SMBUS_EMUL includes all the SMBus transactions (with the
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| H A D | smbus-protocol.rst | 2 The SMBus Protocol
17 SMBus adapters and I2C adapters (the SMBus command set is automatically
67 SMBus Receive Byte
82 SMBus Send Byte
97 SMBus Read Byte
110 SMBus Read Word
128 SMBus Write Byte
144 SMBus Write Word
174 SMBus Block Read
191 SMBus Block Write
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| H A D | i2c-stub.rst | 8 This module is a very simple fake I2C/SMBus driver. It implements six
9 types of SMBus commands: write quick, (r/w) byte, (r/w) byte data, (r/w)
10 word data, (r/w) I2C block data, and (r/w) SMBus block data.
13 driver, which will then only react to SMBus commands to these addresses.
25 SMBus block command support is disabled by default, and must be enabled
29 SMBus block commands must be written to configure an SMBus command for
30 SMBus block operations. Writes can be partial. Block read commands always
47 The SMBus addresses to emulate chips at.
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| H A D | summary.rst | 2 Introduction to I2C and SMBus
20 SMBus (System Management Bus) is based on the I2C protocol, and is mostly
22 SMBus, but some SMBus protocols add semantics beyond what is required to
23 achieve I2C branding. Modern PC mainboards rely on SMBus. The most common
24 devices connected through SMBus are RAM modules configured using I2C EEPROMs,
27 Because the SMBus is mostly a subset of the generalized I2C bus, we can
29 meet both SMBus and I2C electrical constraints; and others which can't
30 implement all the common SMBus protocol semantics or messages.
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| H A D | fault-codes.rst | 6 codes in the I2C/SMBus stack.
26 I2C and SMBus fault codes
55 fault is only reported on read transactions; the SMBus slave
61 Returned by SMBus adapters when the bus was busy for longer
102 doesn't support SMBus block transfers is asked to execute
115 or SMBus (or chip-specific) protocol specifications. One
116 case is when the length of an SMBus block data response
117 (from the SMBus slave) is outside the range 1-32 bytes.
127 SMBus adapters may return it when an operation took more
128 time than allowed by the SMBus specification; for example,
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| H A D | dev-interface.rst | 58 Well, you are all set up now. You can now use SMBus commands or plain
59 I2C to communicate with your device. SMBus commands are preferred if
66 /* Using SMBus commands */
92 Note that only a subset of the I2C and SMBus protocols can be achieved by
118 Selects SMBus PEC (packet error checking) generation and verification
120 Used only for SMBus transactions. This request only has an effect if the
151 You can do SMBus level transactions (see documentation file smbus-protocol.rst
195 device you want to access) and I2C_PEC (enable or disable SMBus error
201 performs an SMBus transaction using i2c-core-smbus.c:i2c_smbus_xfer().
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| /openbmc/linux/Documentation/i2c/busses/ |
| H A D | i2c-amd8111.rst | 6 * AMD-8111 SMBus 2.0 PCI interface
20 00:07.2 SMBus: Advanced Micro Devices [AMD] AMD-8111 SMBus 2.0 (rev 02)
21 Subsystem: Advanced Micro Devices [AMD] AMD-8111 SMBus 2.0
32 SMBus 2.0 Support
41 Note that for the 8111, there are two SMBus adapters. The SMBus 2.0 adapter
42 is supported by this driver, and the SMBus 1.0 adapter is supported by the
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| H A D | i2c-i801.rst | 72 0x01 disable SMBus PEC
76 0x20 disable SMBus Host Notify
98 The SMBus controller is function 3 in device 1f. Class 0c05 is SMBus Serial
102 SMBus controller.
117 SMBus 2.0 Support
129 Hidden ICH SMBus
148 In order to unhide the SMBus, we need to change the value of a PCI
152 and you think there's something interesting on the SMBus (e.g. a
170 that the unhidden SMBus doesn't conflict with e.g. ACPI.
179 anything interesting on your hidden ICH SMBus.
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| H A D | i2c-piix4.rst | 45 SMBus - you can not access it on I2C levels. The good news is that it
46 natively understands SMBus commands and you do not have to worry about
58 find such an entry, you have a PIIX4 SMBus controller.
60 On some computers (most notably, some Dells), the SMBus is disabled by
67 'force' does, but it will also set a new base I/O port address. The SMBus
74 The PIIX/PIIX3 does not implement an SMBus or I2C bus, so you can't use
78 identical to the PIIX4 in I2C/SMBus support.
81 PIIX4-compatible SMBus controllers. If your BIOS initializes the
83 an "Auxiliary SMBus Host Controller".
86 to change the SMBus Interrupt Select register so the SMBus controller uses
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| H A D | i2c-ismt.rst | 19 and never needs to be changed. However, some SMBus analyzers are too slow for
37 The S12xx series of SOCs have a pair of integrated SMBus 2.0 controllers
43 00:13.0 System peripheral: Intel Corporation Centerton SMBus 2.0 Controller 0
44 00:13.1 System peripheral: Intel Corporation Centerton SMBus 2.0 Controller 1
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| H A D | i2c-amd756.rst | 27 Note that for the 8111, there are two SMBus adapters. The SMBus 1.0 adapter
28 is supported by this driver, and the SMBus 2.0 adapter is supported by the
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| H A D | i2c-viapro.rst | 39 Forcibly enable the SMBus controller. DANGEROUS!
41 Forcibly enable the SMBus at the given address. EXTREMELY DANGEROUS!
46 i2c-viapro is a true SMBus host driver for motherboards with one of the
70 enable ACPI / SMBus or even USB.
76 The CX700/VX800/VX820 additionally appears to support SMBus PEC, although
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| H A D | i2c-nforce2.rst | 23 AMD-8111 SMBus 2.0 adapter.
37 00:01.1 SMBus: nVidia Corporation: Unknown device 0064 (rev a2)
49 The SMBus adapter in the nForce2 chipset seems to be very similar to the
50 SMBus 2.0 adapter in the AMD-8111 south bridge. However, I could only get
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| H A D | i2c-sis96x.rst | 22 This SMBus only driver is known to work on motherboards with the above
24 proper datasheet from SiS. The SMBus registers are assumed compatible with
33 00:02.1 SMBus: Silicon Integrated Systems [SiS]: Unknown device 0016
39 00:02.1 SMBus: Silicon Integrated Systems [SiS]: Unknown device 0016
57 * The driver does not support SMBus block reads/writes; I may add them if a
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| H A D | i2c-taos-evm.rst | 7 This is a driver for the evaluation modules for TAOS I2C/SMBus chips.
8 The modules include an SMBus master with limited capabilities, which can
37 Only 4 SMBus transaction types are supported by the TAOS evaluation
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| /openbmc/linux/Documentation/driver-api/ |
| H A D | i2c.rst | 1 I\ :sup:`2`\ C and SMBus Subsystem
29 The System Management Bus (SMBus) is a sibling protocol. Most SMBus
31 for SMBus, and it standardizes particular protocol messages and idioms.
32 Controllers that support I2C can also support most SMBus operations, but
33 SMBus controllers don't support all the protocol options that an I2C
34 controller will. There are functions to perform various SMBus protocol
35 operations, either using I2C primitives or by issuing SMBus commands to
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| /openbmc/linux/arch/arm/boot/dts/aspeed/ |
| H A D | aspeed-bmc-asrock-x570d4u.dts | 160 /* SMBus on auxiliary panel header (AUX_PANEL1) */
165 /* Hardware monitoring SMBus */
175 /* PSU SMBus (PSU_SMB1) */
193 /* SMBus on PCI express 16x slot */
200 /* SMBus on PCI express 8x slot */
214 /* SMBus on PCI express 1x slot */
223 /* SMBus on BMC connector (BMC_SMB_1) */
228 /* FRU and SPD EEPROM SMBus */
249 /* SMBus on intelligent platform management bus header (IPMB_1) */
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| /openbmc/linux/drivers/i2c/ |
| H A D | Kconfig | 14 many micro controller applications and developed by Philips. SMBus,
19 Both I2C and SMBus are supported here. You will need this for
98 tristate "SMBus-specific protocols" if !I2C_HELPER_AUTO
100 Say Y here if you want support for SMBus extensions to the I2C
102 the SMBus Alert protocol and the SMBus Host Notify protocol.
111 tristate "I2C/SMBus Test Stub"
114 This module may be useful to developers of SMBus client drivers,
142 multi-master, SMBus Host Notify, etc. Please read
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| /openbmc/docs/designs/ |
| H A D | nvmemi-over-smbus.md | 1 ### NVMe-MI over SMBus
11 SMBus directly. The NVMe drive can provide its information or status, like
19 via SMBus directly. [1]. This command uses SMBus Block Read protocol specified
20 by the SMBus specification. [2].
29 [2] System Management Bus (SMBus) Specification Version 3.0 20 Dec 2014
160 3. Send a NVMe-MI command via SMBus Block Read protocol by bus ID of target
197 SMBus directly is much simpler than NVMe-MI over MCTP protocol.
206 This implementation is to use NVMe-MI-Basic command over SMBus and then set the
207 response data to D-bus. Testing will send SMBus command to the drives to get the
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| /openbmc/linux/Documentation/hwmon/ |
| H A D | lm90.rst | 510 * SMBus PEC support for Write Byte and Receive Byte transactions.
515 * SMBus PEC support for Write Byte and Receive Byte transactions.
520 * SMBus PEC support
595 SMBus Alert Support
602 Semiconductor chips (NCT1008) do not implement the SMBus alert protocol
615 ADM1032 chip. However, in the case of a combined transaction (SMBus Read
619 value differs from what the SMBus master expects, and all reads fail.
622 the bus supports the SMBus Send Byte and Receive Byte transaction types.
624 SMBus Read Byte, and PEC will work properly.
626 Additionally, the ADM1032 doesn't support SMBus Send Byte with PEC.
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| H A D | sbrmi.rst | 18 The SMBus address is really 7 bits. Some vendors and the SMBus
39 (SB-RMI) module from the external SMBus master that can be used to report socket
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| /openbmc/linux/Documentation/devicetree/bindings/hwmon/ |
| H A D | amd,sbrmi.yaml | 15 SB Remote Management Interface (SB-RMI) is an SMBus compatible
29 I2C bus address of the device as specified in Section SBI SMBus Address
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| /openbmc/phosphor-host-ipmid/docs/ |
| H A D | oem-extension-numbering.md | 97 [Linux Kernel SMBus Protocol](https://www.kernel.org/doc/Documentation/i2c/smbus-protocol),
102 - Goal is to support SMBus v2 32-byte data block length limit; but easily
104 [SMBus v3](http://smbus.org/specs/SMBus_3_0_20141220.pdf).
106 - PEC refers to SMBus Packet Error Check.
108 - SMBus address resolution, alerts, and non-standard protocols not supported. So
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| /openbmc/linux/drivers/i2c/busses/ |
| H A D | Kconfig | 9 comment "PC SMBus host controller drivers"
167 tristate "Intel SCH SMBus 1.0"
178 tristate "Intel iSMT SMBus Controller"
182 iSMT SMBus host controller interface.
342 tristate "SMBus Control Method Interface"
353 comment "Mac SMBus host controller drivers"
439 Au1550/Au1200/Au1300 SMBus interface.
914 tristate "PA Semi SMBus interface"
920 tristate "Apple SMBus platform driver"
1349 comment "Other I2C/SMBus bus drivers"
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| /openbmc/openbmc/poky/meta/recipes-devtools/i2c-tools/ |
| H A D | i2c-tools_4.3.bb | 3 …p dumper, register-level SMBus access helpers, EEPROM decoding scripts, EEPROM programming tools, …
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