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Searched refs:SIFIVE_U_PRCI_PLLCFG0_FSE (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/hw/misc/
H A Dsifive_u_prci.c73 s->corepllcfg0 |= SIFIVE_U_PRCI_PLLCFG0_FSE; in sifive_u_prci_write()
80 s->ddrpllcfg0 |= SIFIVE_U_PRCI_PLLCFG0_FSE; in sifive_u_prci_write()
90 s->gemgxlpllcfg0 |= SIFIVE_U_PRCI_PLLCFG0_FSE; in sifive_u_prci_write()
138 SIFIVE_U_PRCI_PLLCFG0_DIVQ | SIFIVE_U_PRCI_PLLCFG0_FSE | in sifive_u_prci_reset()
141 SIFIVE_U_PRCI_PLLCFG0_DIVQ | SIFIVE_U_PRCI_PLLCFG0_FSE | in sifive_u_prci_reset()
144 SIFIVE_U_PRCI_PLLCFG0_DIVQ | SIFIVE_U_PRCI_PLLCFG0_FSE | in sifive_u_prci_reset()
/openbmc/qemu/include/hw/misc/
H A Dsifive_u_prci.h49 #define SIFIVE_U_PRCI_PLLCFG0_FSE (1 << 25) macro