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Searched refs:SIFIVE_U_DEV_UART0 (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/include/hw/riscv/
H A Dsifive_u.h87 SIFIVE_U_DEV_UART0, enumerator
/openbmc/qemu/hw/riscv/
H A Dsifive_u.c78 [SIFIVE_U_DEV_UART0] = { 0x10010000, 0x1000 },
486 (long)memmap[SIFIVE_U_DEV_UART0].base); in create_fdt()
490 0x0, memmap[SIFIVE_U_DEV_UART0].base, in create_fdt()
491 0x0, memmap[SIFIVE_U_DEV_UART0].size); in create_fdt()
842 sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART0].base, in sifive_u_soc_realize()