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Searched refs:SIFIVE_U_DEV_QSPI0 (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/include/hw/riscv/
H A Dsifive_u.h90 SIFIVE_U_DEV_QSPI0, enumerator
/openbmc/qemu/hw/riscv/
H A Dsifive_u.c82 [SIFIVE_U_DEV_QSPI0] = { 0x10040000, 0x1000 },
376 (long)memmap[SIFIVE_U_DEV_QSPI0].base); in create_fdt()
385 0x0, memmap[SIFIVE_U_DEV_QSPI0].base, in create_fdt()
386 0x0, memmap[SIFIVE_U_DEV_QSPI0].size); in create_fdt()
391 (long)memmap[SIFIVE_U_DEV_QSPI0].base); in create_fdt()
929 memmap[SIFIVE_U_DEV_QSPI0].base); in sifive_u_soc_realize()