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Searched refs:SIFIVE_U_DEV_L2LIM (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/include/hw/riscv/
H A Dsifive_u.h84 SIFIVE_U_DEV_L2LIM, enumerator
/openbmc/qemu/hw/riscv/
H A Dsifive_u.c75 [SIFIVE_U_DEV_L2LIM] = { 0x8000000, 0x2000000 },
583 start_addr = memmap[SIFIVE_U_DEV_L2LIM].base; in sifive_u_machine_init()
822 memmap[SIFIVE_U_DEV_L2LIM].size, &error_fatal); in sifive_u_soc_realize()
823 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_L2LIM].base, in sifive_u_soc_realize()