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Searched refs:SIFIVE_U_DEV_GEM_MGMT (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/include/hw/riscv/
H A Dsifive_u.h97 SIFIVE_U_DEV_GEM_MGMT, enumerator
/openbmc/qemu/hw/riscv/
H A Dsifive_u.c87 [SIFIVE_U_DEV_GEM_MGMT] = { 0x100a0000, 0x1000 },
410 0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].base, in create_fdt()
411 0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].size); in create_fdt()
919 memmap[SIFIVE_U_DEV_GEM_MGMT].base, memmap[SIFIVE_U_DEV_GEM_MGMT].size); in sifive_u_soc_realize()