Searched refs:SIFIVE_U_DEV_DEBUG (Results 1 – 2 of 2) sorted by relevance
| /openbmc/qemu/include/hw/riscv/ | ||
| H A D | sifive_u.h | 79 SIFIVE_U_DEV_DEBUG, enumerator |
| /openbmc/qemu/hw/riscv/ | ||
| H A D | sifive_u.c | 70 [SIFIVE_U_DEV_DEBUG] = { 0x0, 0x100 }, |