Searched refs:SI5351_OUTPUT_CLK_DIVBY4 (Results 1 – 2 of 2) sorted by relevance
110 #define SI5351_OUTPUT_CLK_DIVBY4 (3<<2) macro
626 SI5351_OUTPUT_CLK_DIVBY4) == SI5351_OUTPUT_CLK_DIVBY4) { in si5351_msynth_recalc_rate()780 SI5351_OUTPUT_CLK_DIVBY4, in si5351_msynth_set_rate()781 (divby4) ? SI5351_OUTPUT_CLK_DIVBY4 : 0); in si5351_msynth_set_rate()