Searched refs:SH_RD (Results 1 – 2 of 2) sorted by relevance
/openbmc/linux/arch/riscv/kernel/ |
H A D | traps_misaligned.c | 98 #define SH_RD 7 macro 119 #define RVC_RS1S(insn) (8 + RV_X(insn, SH_RD, 3)) 143 #define SET_RD(insn, regs, val) (*REG_PTR(insn, SH_RD, regs) = (val)) 241 insn = RVC_RS2S(insn) << SH_RD; in handle_misaligned_load() 243 ((insn >> SH_RD) & 0x1f)) { in handle_misaligned_load() 250 insn = RVC_RS2S(insn) << SH_RD; in handle_misaligned_load() 252 ((insn >> SH_RD) & 0x1f)) { in handle_misaligned_load() 258 insn = RVC_RS2S(insn) << SH_RD; in handle_misaligned_load() 266 insn = RVC_RS2S(insn) << SH_RD; in handle_misaligned_load()
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/openbmc/linux/arch/riscv/kvm/ |
H A D | vcpu_insn.c | 83 #define SH_RD 7 macro 105 #define RVC_RS1S(insn) (8 + RV_X(insn, SH_RD, 3)) 129 #define SET_RD(insn, regs, val) (*REG_PTR(insn, SH_RD, regs) = (val)) 240 if ((insn >> SH_RD) & MASK_RX) in kvm_riscv_vcpu_csr_return() 513 insn = RVC_RS2S(insn) << SH_RD; in kvm_riscv_vcpu_mmio_load() 515 ((insn >> SH_RD) & 0x1f)) { in kvm_riscv_vcpu_mmio_load() 522 insn = RVC_RS2S(insn) << SH_RD; in kvm_riscv_vcpu_mmio_load() 524 ((insn >> SH_RD) & 0x1f)) { in kvm_riscv_vcpu_mmio_load() 631 ((insn >> SH_RD) & 0x1f)) { in kvm_riscv_vcpu_mmio_store() 639 ((insn >> SH_RD) & 0x1f)) { in kvm_riscv_vcpu_mmio_store()
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